Efficient on-chip crosstalk avoidance CODEC design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 4, 2009, Pages 551-560

  Duan, Chunjie ^a   Cordero Calle, Victor H ^b   Khatri, Sunil P ^b  

^a MITSUBISHI ELECTRIC RESEARCH LABORATORIES   (United States)

^b Texas AandM University   (United States)

Author keywords

CODEC; Crosstalk; Fibonacci number; On chip bus

Indexed keywords

AVAILABILITY; BUSES; CROSSTALK; DESIGN; NUMBER THEORY; OPTICAL DEVICES; OPTIMIZATION; THICKNESS MEASUREMENT;

AREA OVERHEADS; CIRCUIT PERFORMANCE; CODE-WORDS; CODEC; CODEC DESIGNS; CODING SCHEMES; CONSTRUCTION SCHEMES; CROSSTALK AVOIDANCES; DATA PATTERNS; DESIGN COMPLEXITY; ENERGY CONSUMPTION; FIBONACCI NUMBER; FORBIDDEN PATTERNS; INTERCONNECT DELAYS; LIMITING FACTORS; MAPPING SCHEMES; NONLINEAR NATURES; ON-CHIP BUS; ON-CHIP CROSSTALKS; OPTIMAL PERFORMANCE; OPTIMIZATION SCHEMES; SUB MICROMETERS; SYSTEMATIC MAPPINGS;

CODES (SYMBOLS);

EID: 62949217527     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2005313     Document Type: Article

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