Design of on-chip error correction systems for multilevel NOR and NAND flash memories

IET Circuits, Devices and Systems

Volumn 1, Issue 3, 2007, Pages 241-249

  Sun, F ^a   Devarajan, S ^a   Rose, K ^a   Zhang, T ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CAPACITY; DATA STORAGE EQUIPMENT; FLASH MEMORY; NAND CIRCUITS; TRELLIS CODES;

NON-TRIVIAL MODULATION PROCESS; SHORT BLOCK LENGTH; TRELLIS CODED MODULATION (TCM);

ERROR CORRECTION;

EID: 34547345637     PISSN: 1751858X     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cds:20060275     Document Type: Article

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