Methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 172-175

  Mehrotra, Vikas ^a   Sam, Shiou Lin ^a   Boning, Duane ^a   Chandrakasan, Anantha ^a   Vallishayee, Rakesh ^a   Nassif, Sani ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; COMPUTER AIDED DESIGN; COPPER; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; INTERCONNECTION NETWORKS;

ALUMINUM AND COPPER INTERCONNECT TECHNOLOGY; CLOCK SKEW; INTERCONNECT DELAY; INTERCONNECT VARIATION; SPATIAL PATTERN DEPENDENT VARIATION;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0033719785     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)