The impact of size effects and copper interconnect process variations on the maximum critical path delay of single and multi-core microprocessors

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

Volumn , Issue , 2007, Pages 40-42

  Lopez, Gerald ^a   Murali, Raghunath ^a   Sarvari, Reza ^a   Bowman, Keith ^b   Davis, Jeffrey ^a   Meindl, James ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b INTEL RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COPPER COMPOUNDS; ELECTRIC CONDUCTIVITY; ELECTRIC CONDUCTORS; MICROPROCESSOR CHIPS; MONTE CARLO METHODS;

CONDUCTOR RESISTIVITY; COPPER INTERCONNECT PROCESS VARIATIONS; MULTI-CORE MICROPROCESSORS; SIZE EFFECTS;

OPTICAL INTERCONNECTS;

EID: 34748880817     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iitc.2007.382346     Document Type: Conference Paper

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