Architecture of the scalable communications core's network on chip

IEEE Micro

Volumn 27, Issue 5, 2007, Pages 62-74

  Ilitzky, David Arditti ^a   Hoffman, Jeffrey D ^b   Chun, Anthony ^b   Esparza, Brando Perez ^a  

^a Intel's Communication Research Center   (Mexico)

^b INTEL CORPORATION   (United States)

Author keywords

Communication; Mobile communications; Multicore architectures; Networking; on chip interconnection networks; Parallel architectures; Parallel processing; Wide area networks; Wide area networks; Wireless; Wireless communications

Indexed keywords

COMPUTER ARCHITECTURE; MOBILE TELECOMMUNICATION SYSTEMS; NETWORK PROTOCOLS; PACKET NETWORKS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; WIDE AREA NETWORKS; WIRELESS TELECOMMUNICATION SYSTEMS;

MULTICORE ARCHITECTURE; ON-CHIP INTERCONNECTION NETWORKS; PROGRAMMABLE ACCELERATORS;

MICROPROCESSOR CHIPS;

EID: 36849096008     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2007.4378784     Document Type: Article

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