An overview of on-chip interconnect variation

International Workshop on System Level Interconnect Prediction, SLIP

Volumn 2006, Issue , 2006, Pages 27-28

  Scheffer, Lou ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Causes of variability; Design rules; On chip variation

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; LITHOGRAPHY; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SILICON WAFERS;

DESIGN RULES; METAL LAYERS; ON-CHIP VARIATION; VARIABILITY CAUSES;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 33750928791     PISSN: None     EISSN: 15445631     Source Type: Conference Proceeding    
DOI: 10.1145/1117278.1117284     Document Type: Conference Paper

References (0)