On-chip interconnection networks of the TRIPS chip

IEEE Micro

Volumn 27, Issue 5, 2007, Pages 41-50

  Gratz, Paul ^a   Kim, Changkyu ^b   Sankaralingam, Karthikeyan ^c   Hanson, Heather ^d   Shivakumar, Premkishore ^a   Keckler, Stephen W ^a   Burger, Doug ^e  

^a The University of Texas at Austin   (United States)

^b INTEL CORPORATION   (United States)

^c UNIVERSITY OF WISCONSIN MADISON   (United States)

^d IBM   (United States)

^e UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Communication; Distributed architectures; Distributed processing; Interconnection networks; Multicore architectures; Networking; On chip interconnection networks; Packet switching; Packet switching networks

Indexed keywords

BANDWIDTH; DISTRIBUTED COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; PACKET SWITCHING;

DISTRIBUTED ARCHITECTURE; MULTICORE ARCHITECTURE; ON-CHIP INTERCONNECTION NETWORKS;

INTERCONNECTION NETWORKS;

EID: 36849013038     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2007.4378782     Document Type: Article

References (6)

1. D. Burger et al., "Scaling to the End of Silicon with EDGE Architectures," Computer, vol. 37, no. 7, July 2004, pp. 44-55.
2. K. Sankaralingam et al., "The Distributed Microarchitecture of the TRIPS Prototype Processor," Proc. 39th ACM/IEEE Int'l Symp. Microarchitecture (MICRO 06), IEEE CS Press, 2006, pp. 480-491.
3. P. Gratz et al., "Implementation and Evaluation of a Dynamically Routed Processor Operand Network," Proc. 1st Int'l Symp. Networks-on-Chip (NOCS 07), IEEE CS Press, 2007, pp. 7-17.
4. A.J. KleinOsowski and D.J. Lilja, "Minne-SPEC: A New SPEC Benchmark Workload for Simulation Based Computer Architecture Research," Computer Architecture Letters, vol. 1, no. 1, Jan. 2002, p. 7.
5. T. Sherwood, E. Perelman, and B. Calder, "Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications," Proc. Int'l Symp. Parallel Architectures and Compilation Techniques (PACT 01), IEEE CS Press, 2001, pp. 3-15.
6. P. Gratz et al., "Implementation and Evaluation of On-Chip Network Architectures," Proc. IEEE Int'l Conf. Computer Design (ICCD 06), IEEE Press, 2006, http://www.iccd-conference.org/proceedings/2006/ paper_174.pdf.