An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 1, 2008, Pages 29-41

  Vangal, Sriram R ^a   Howard, Jason ^a   Ruhl, Gregory ^a   Dighe, Saurabh ^a   Wilson, Howard ^a   Tschanz, James ^a   Finan, David ^a   Singh, Arvind ^b   Jacob, Tiju ^b   Jain, Shailendra ^b   Erraguntla, Vasantha ^b   Roberts, Clark ^a   Hoskote, Yatin ^a   Borkar, Nitin ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

^b INTEL TECHNOLOGY INDIA PVT LTD   (India)

Author keywords

CMOS digital integrated circuits; crossbar router and network on chip (NoC); floating point unit; interconnection; leakage reduction; MAC; multiply accumulate

Indexed keywords

EID: 85008053864     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.2007.910957     Document Type: Article

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