Computer architecture techniques for power-efficiency

Synthesis Lectures on Computer Architecture

Volumn 4, Issue , 2008, Pages 1-218

  Kaxiras, Stefanos ^a   Martonosi, Margaret ^b  

^a UNIVERSITY OF PATRAS   (Greece)

^b PRINCETON UNIVERSITY   (United States)

Author keywords

Computer architecture; Computer energy consumption; Computer hardware; Computer power consumption; Computer power efficiency; Dynamic power; Dynamic voltage frequency scaling; Leakage power; Low power computer design; Static power

Indexed keywords

ARCHITECTURE; COMPUTER SCIENCE; COMPUTER SYSTEMS; COMPUTERS; ELECTRIC POWER UTILIZATION; PROCESS DESIGN; PROCESS ENGINEERING;

APPLIED (CO); ARCHITECTURAL TECHNIQUES; ARCHITECTURE TECHNIQUES; DESIGN CONSTRAINTS; DESIGN PROCESSES; DYNAMIC POWER; MEMORY HIERARCHIES; OPERATING FREQUENCIES; PERFORMANCE GAINS; POWER DENSITY (PD); POWER DISSIPATIONS; POWER EFFICIENCIES; POWER EFFICIENT; PROCESSOR PERFORMANCE; STATIC POWER DISSIPATION; TOPIC AREAS; TRANSISTOR COUNTS; WIDE-RANGE;

COMPUTER ARCHITECTURE;

EID: 46649098676     PISSN: 19353235     EISSN: 19353243     Source Type: Book Series    
DOI: 10.2200/S00119ED1V01Y200805CAC004     Document Type: Article

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