New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors

IBM Journal of Research and Development

Volumn 47, Issue 5-6, 2003, Pages 653-670

  Brooks, David ^a   Bose, Pradip ^b   Srinivasan, Vijaylakshmi ^b   Gschwind, Michael K ^b   Emma, Philip G ^b   Rosenfield, Michael G ^c  

^a HARVARD UNIVERSITY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; OBJECT ORIENTED PROGRAMMING;

ENERGY FUNCTIONS; POWER CONSUMPTION;

MICROPROCESSOR CHIPS;

EID: 0346898058     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.475.0653     Document Type: Article

References (33)

1. M. K. Gowan, L. L. Biro, and D. B. Jackson, "Power Considerations in the Design of the Alpha 21264 Microprocessor," Proceedings of the IEEE/ACM Design Automation Conference, 1998, pp. 726-731.
2. D. Brooks, J.-D. Wellman, P. Bose, and M. Martonosi, "Power-Performance Modeling and Tradeoff Analysis for a High-End Microprocessor," presented at the Workshop on Power-Aware Computer Systems (PACS'00, held in conjunction with ASPLOS-IX), Cambridge, MA, November 2000; also appeared as Lecture Notes on Computer Science (LCNS), Vol. 2008, 2001, pp. 126-136.
3. D. Brooks, J.-D. Wellman, P. Bose, and M. Martonosi, "Power-Performance Modeling and Tradeoff Analysis for a High-End Microprocessor," presented at the Workshop on Power-Aware Computer Systems (PACS'00, held in conjunction with ASPLOS-IX), Cambridge, MA, November 2000; also appeared as Lecture Notes on Computer Science (LCNS), Vol. 2008, 2001, pp. 126-136.
4. J. S. Neely, H. H. Chen, S. G. Walker, J. Venuto, and T. J. Bucelot, "CPAM: A Common Power Analysis Methodology for High Performance Design," Proceedings of the 9th Topical Meeting on Electrical Performance of Electronic Packaging, Scottsdale, AZ, October 2000, pp. 303-306.
5. M. Moudgill, J.-D. Wellman, and J. Moreno, "Environment for PowerPC Microarchitecture Exploration," IEEE Micro 19, No. 3, 15-25 (May/June 1999); see also http://www.research.ibm.com/MET/.
6. M. Moudgill, P. Bose, and J. Moreno, "Validation of Turandot, a Fast Processor Model for Microarchitecture Exploration," Proceedings of the IEEE International Performance, Computing and Communication Conference, February 1999, pp. 451-457.
7. F. P. O'Connell and S. W. White, "POWER3: The Next Generation of PowerPC Processors," IBM J. Res. & Dev. 44, No. 6, 873-884 (November 2000).
8. J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, "POWER4 System Microarchitecture," IBM J. Res. & Dev. 46, No. 1, 1-116 (January 2002).
9. S. Borkar, "Design Challenges of Technology Scaling," IEEE Micro 19, No. 4, 23-29 (July/August 1999).
10. Standard Performance Evaluation Corporation (SPEC), Warrentown, VA; see http://www.spec.org/ for details.
11. Benchmark C of the Transaction Processing Recording Council (TPC), San Francisco, CA; see http://www.tpc.org/ for details.
12. D. M. Brooks, P. Bose, S. E. Schuster, H. Jacobson, P. N. Kudva, A. Buyuktosunoglu, J.-D. Wellman, V. Zyuban, M. Gupta, and P. W. Cook, "Power-Aware Microarchitectures: Design and Modeling Challenges for Next-Generation Microprocessors," IEEE Micro 20, No. 6, 26-44 (November 2000).
13. V. Zyuban and P. Strenski, "Unified Methodology for Resolving Power-Performance Tradeoffs of the Microarchitectural and Circuit Levels," Proceedings of the International Symposium on Low-Power Electronics and Design, August 2002, pp. 166-171.
14. V. Zyuban and P. N. Strenski, "Balancing Hardware Intensity in Microprocessor Pipelines," IBM J. Res. & Dev. 47, No. 5/6, 585-598 (this issue, September/November 2003).
15. U. Ko, P. T. Balsara, and A. K. Nanda, "Energy Optimization of Multilevel Cache Architectures for RISC and CISC Processors," IEEE Trans. VLSI Syst. 6, No. 2, 299-308 (June 1998).
16. V. Srinivasan, D. Brooks, M. Gschwind, P. Bose, P. Emma, V. Zyuban, and P. Strenski, "Optimizing Pipelines for Power and Performance," Proceedings of the International Symposium on Microarchitecture (MICRO-35), November 2002, pp. 333-344.
17. A. Hartstein and T. R. Puzak, "The Optimum Pipeline Depth for a Microprocessor," Proceedings of the 29th International Symposium on Computer Architecture (ISCA-29), May 2002, pp. 7-13.
18. M. S. Hrishikesh, D. Burger, N. P. Jouppi, S. W. Keckler, K. I. Farkas, and P. Shivakumar, "The Optimal Logic Depth per Pipeline Stage Is 6 to 8 FO4 Inverter Delays," Proceedings of the 29th International Symposium on Computer Architecture (ISCA-29), May 2002, pp. 14-24.
19. E. Sprangle and D. Carmean, "Increasing Processor Performance by Implementing Deeper Pipelines," Proceedings of the 29th International Symposium on Computer Architecture (ISCA-29), May 2002, pp. 25-34.
20. R. Gonzalez and M. Horowitz, "Energy Dissipation in General Purpose Microprocessors," IEEE J. Solid-State Circuits 31, No. 9, 1277-1284 (1996).
21. T. Conte, K. Menezes, and S. Sathaye, "A Technique to Determine Power-Efficient, High Performance Super Scalar Processors," Proceedings of the 28th Hawaii International Conference on System Science, January 1995, Vol. 1, pp. 324-333.
22. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural Level Power Analysis and Optimizations," Proceedings of the International Symposium on Computer Architecture (ISCA), June 2000, pp. 83-94.
23. D. Brooks, "Design and Modeling of Power-Efficient Computer Architectures," Ph.D. dissertation, Princeton University, November 2001.
24. N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. S. Kim, and W. Ye, "Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower," Proceedings of the International Symposium on Computer Architecture (ISCA), June 2000, pp. 95-106.
25. 2EST: A Thermal Enabled Multi-Model Power/Performance ESTimator," Digest of Technical Papers, Workshop on Power-Aware Computer Systems (PACS'00), Cambridge, MA, November 2000; also appeared as Lecture Notes on Computer Science (LCNS), Vol. 2008, 2001, pp. 112-125.
26. 2EST: A Thermal Enabled Multi-Model Power/Performance ESTimator," Digest of Technical Papers, Workshop on Power-Aware Computer Systems (PACS'00), Cambridge, MA, November 2000; also appeared as Lecture Notes on Computer Science (LCNS), Vol. 2008, 2001, pp. 112-125.
27. S. H. Gunther, F. Binns, D. Carmean, and J. C. Hall, "Managing the Impact of Increasing Microprocessor Power Consumption," Intel Technol. J., Q1, 2001; see http://www.intel.com/technology/itj/q12001/articles/art_4.html.
28. D. Burger and T. Austin, "The SimpleScalar Tool Set, Version 2.0," Technical Report TR-1342, University of Wisconsin, June 1997.
29. A. Aharon, A. Bar-David, B. Dorfman, E. Gofman, M. Leibowitz, and V. Schwartzburd, "Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-Random Test Program Generator," IBM Syst. J. 30, No. 4, 527-537 (April 1991).
30. M. Kantrowitz and L. M. Noack, "Functional Verification of a Multiple Issue, Pipelined, Super Scalar Alpha Processor - the Alpha 21164 CPU Chip," Proc. Digital Tech. J. 7, No. 1, 136-144 (1995).
31. B. Black and J. Shen, "Calibration of Microprocessor Performance Models," IEEE Computer 31, No. 5, 59-65 (May 1998).
32. D. Brooks, M. Martonosi, and P. Bose, "Abstraction via Separable Components: An Empirical Study of Absolute and Relative Accuracy in Processor Performance Modeling," Research Report RC-21909, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, December 2000.
33. P. Bose, "Testing for Function and Performance: Towards an Integrated Processor Validation Methodology," J. Electron. Testing: Theory & Appl. 16, 29-48 (2000).