Counter-based cache replacement algorithms

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn 2005, Issue , 2005, Pages 61-68

  Kharbutli, Mazen ^a   Solihin, Yan ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALTERNATIVE REPLACEMENT ALGORITHMS; ASSOCIATIVE CACHES; LEAST RECENTLY USED (LRU);

ALGORITHMS; BENCHMARKING; OPTIMAL SYSTEMS; PROBLEM SOLVING; SET THEORY; THRESHOLD ELEMENTS;

BUFFER STORAGE;

EID: 33748558760     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.41     Document Type: Conference Paper

References (16)

1. L. A. Belady. A study of replacement algorithms for virtual-storage computers. IBM Systems Journal, 1966.
2. K. Beyls and E. D'Hollander. Compile-Time Cache Hint Generation for EPIC architectures. In 2nd Workshop on Explicitly Parallel Instruction Computing Architecture and Compilers, 2002.
3. G. Chen, N. Vijaykrishnan, M. Kandemir, M. Irwin, and M. Wolczko. Tracking Object Life Cycle for Leakage Energy Optimization. In Proc. of the ISSS/CODES joint conference, 2003.
4. Z. Hu, S. Kaxiras, and M. Martonosi. Timekeeping in the memory system: predicting and optimizing memory behavior. In 29th Intl. Symp. on Computer Architecture, 2002.
5. S. Kaxiras, Z. Hu, and M. Martonosi. Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In Intl. Symp. on Computer Architecture, pages 240-251, 2001.
6. V. Krishnan and J. Torrellas. A Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors. In Intl. Conf. on Parallel Architectures and Compilation Techniques, pages 286-293, 1998.
7. A.-C. Lai and B. Falsafi. Selective, accurate, and timely self-invalidation using last-touch prediction. In 27th Intl. Symp. on Computer Architecture, 2000.
8. A.-C. Lai, C. Fide, and B. Falsafi. Dead block prediction and dead block correlating prefetchers. In 28th Intl. Symp. on Computer Architecture, 2001.
9. J. Lee, Y. Solihin, and J. Torrellas. Automatically Mapping Code on an Intelligent Memory Architecture. In 7th Intl. Symp. on High Performance Computer Architecture, 2001.
10. W.-F. Lin and S. K. Reinhardt. Predicting last-touch references under optimal replacement. University of Michigan Tech. Rep. CSE-TR-447-02, 2002.
11. R. L. Mattson, J. Gecsei, D. Slutz, and I. Traiger. Evaluation Techniques for Storage Hierarchies. IBM Systems Journal, 9(2), 1970.
12. M. Takagi and K. Hiraki. Inter-Reference Gap Distribution Replacement: an Improved Replacement Algorithm for Set-Associative Caches. Proc. of the 18th Intl. Conf. on Supercomputing, 2004.
13. Z. Wang, K. McKinley, A. Rosenberg, and C. Weems. Using the Compiler to Improve Cache Replacement Decisions. In Proc. of Intl. Conf. on Parallel Architectures and Compilation Techniques, 2002.
14. W.A.Wong and J-L.Baer. Modified LRU Policies for Improving Second-Level Cache Behavior. In HPCA, 2000.
15. D. A. Wood, M. D. Hill, and R. E. Kessler. A Model for Estimating Trace-Sample Miss Ratios. In Proc. of the ACM SIGMETRICS, 1991.
16. H. Zhou, M. Toburen, E. Rotenberg, and T. Conte. Adaptive Mode Control: A Static-Power-Efficient Cache Design. ACM Trans. on Embedded Computing Systems, 2(3), 2002.