Reducing design complexity of the load/store queue

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2003-January, Issue , 2003, Pages 411-422

  Park, I ^a   Ooi, Chong Liang ^a   Vijaykumar, T N ^a  

^a Purdue University   (United States)

Author keywords

Bandwidth; Buffer storage; CADCAM; Clocks; Computer aided manufacturing; Microarchitecture; Microprocessors; Out of order; Pipelines; Registers

Indexed keywords

ASSOCIATIVE STORAGE; BANDWIDTH; BENCHMARKING; BUFFER STORAGE; CLOCKS; COMPUTER AIDED MANUFACTURING; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; MICROPROCESSOR CHIPS; PIPELINES; PROGRAM PROCESSORS;

BANDWIDTH REQUIREMENT; CACHE HIERARCHIES; CADCAM; DESIGN COMPLEXITY; MEMORY CONSISTENCY MODELS; MICRO ARCHITECTURES; OUT OF ORDER; REGISTERS;

QUEUEING THEORY;

EID: 84944398264     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2003.1253245     Document Type: Conference Paper

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