Design and implementation of the POWER5™ microprocessor

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 670-672

  Clabes, Joachim ^a   Friedrich, Joshua ^a   Sweet, Mark ^a   DiLullo, Jack ^a   Chu, Sam ^a   Plass, Donald ^a   Dawson, James ^a   Muench, Paul ^a   Powell, Larry ^a   Floyd, Michael ^a   Sinharoy, Balaram ^a   Lee, Mike ^a   Goulet, Michael ^a   Wagoner, James ^a   Schwartz, Nicole ^a   Runyon, Steve ^a   Gorman, Gary ^a   Restle, Phillip ^b   Kalla, Ronald ^a   McGill, Joseph ^a   Dodson, Steve ^a   more..

^a IBM   (United States)

^b IBM RESEARCH   (United States)

Author keywords

Clock Gating; Microprocessor Design; Power Reduction; POWER5; Simultaneous Multi threading (SMT); Temperature Sensor

Indexed keywords

CLOCK GATINGS; POWER REDUCTIONS; POWER5; SIMULTANEOUS MULTI-THREADING (SMT); TEMPERATURE SENSORS;

ALGORITHMS; BENCHMARKING; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; GATES (TRANSISTOR); MATHEMATICAL MODELS; MICROELECTROMECHANICAL DEVICES; OPTIMIZATION; RELIABILITY;

MICROPROCESSOR CHIPS;

EID: 4444379636     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. R. Kalla, B. Sinharoy, J. Tendler, "A SMT Implementation in POWER5", Hot Chips, August 15, 2003.
2. P. J. Restle et al, "A Clock Distribution Method for Microprocessors", IEEE JSSC, Vol. 36, pp. 792-799, May 2001.