IATAC: A Smart Predictor to Turn-Off L2 Cache Lines

ACM Transactions on Architecture and Code Optimization

Volumn 2, Issue 1, 2005, Pages 55-77

  Abella, Jaume ^a   Gonzaález, Antonio ^a   Vera, Xavier ^a   O'BOYLE, Michael F P ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

Cache memories; Design; L2 cache; Low power; Performance; Turning off cache lines

Indexed keywords

EID: 85016664946     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1061267.1061271     Document Type: Article

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