Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 207-212

  Keshavarzi, A ^a   Ma, S ^a   Narendra, S ^a   Bloechel, B ^a   Mistry, K ^a   Ghani, T ^a   Borkar, S ^a   De, V ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; ELECTRIC POTENTIAL; ELECTRON TUNNELING; LEAKAGE CURRENTS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SEMICONDUCTOR JUNCTIONS; TRANSISTORS;

REVERSE BODY BIAS (RBB);

CMOS INTEGRATED CIRCUITS;

EID: 0034878684     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383135     Document Type: Conference Paper

References (11)