Efficient techniques for gate leakage estimation

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 100-103

  Rao, R M ^a   Burns, J L ^b   Devgan, A ^b   Brown, R B ^a  

^a University of Michigan   (United States)

^b IBM   (United States)

Author keywords

Circuit analysis; Circuit simulation; CMOS technology; Gate leakage; Leakage current; Pattern analysis; Power generation; SPICE; State estimation; Steady state

Indexed keywords

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; LOW POWER ELECTRONICS; POWER ELECTRONICS; POWER GENERATION; SPICE; STATE ESTIMATION;

CMOS TECHNOLOGY; FUTURE TECHNOLOGIES; GATE LEAKAGES; GATE-LEAKAGE CURRENT; LEAKAGE COMPONENTS; PATTERN ANALYSIS; PROBABILISTIC ANALYSIS; STEADY STATE;

LEAKAGE CURRENTS;

EID: 1542359168     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231843     Document Type: Conference Paper

References (8)

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