Power considerations in the design of the alpha 21264 microprocessor

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 726-731

  Gowan, Michael K ^a   Biro, Larry L ^a   Jackson, Daniel B ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; ELECTRIC LOSSES; INTEGRATED CIRCUIT LAYOUT; TRANSISTORS;

CLOCK NETWORK; CLOCK RATE; DESIGN TEAM; ELECTRICAL DESIGN; HIGH-PERFORMANCE MICROPROCESSORS; THIRD-GENERATION ALPHA MICROPROCESSOR;

INTEGRATED CIRCUIT DESIGN; MICROPROCESSOR CHIPS;

POWER DISSIPATION MANAGEMENT;

EID: 0031641244     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277226     Document Type: Conference Paper

References (6)

1. Dobberpuhl, D., et al., "A 200 MHZ 64b Dual-Issue CMOS Microprocessor, " IEEE Journal of Solid Stale Circuits, vol. 27, no. 11, Nov., 1992.
2. Benschneider, B., et al., "A 300-MHz 64b Quad-Issue CMOS RISC Microprocessor, " IEEE Journal of Solid State Circuits, vol. 30, no. 11, Nov., 1995.
3. Gieseke, B., et al., "A 600 MHZ Supcrscaler RISC Microprocessor With Out-of-Order Execution, " ISSCC Digest of Technical Papers, pp. 222-223, Feb., 1996.
4. Grundmann, W., et al., "Designing High Performance CMOS Microprocessors Using Full Custom Techniques, " Proceedings of the 34, b Design Automation Conference, pp. 722-727, June, 1997.
5. Fair, H. and Bailey, D., "Clocking Design and Analysis for a 600 MHZ Alpha Microprocessor, " ISSCC Digest of Technical Papers, pp. 398-399, Feb., 1998.
6. Kitchin, J., "Statistical Electromigration Risk Budgeting for Reliable Design and Verification in a 300MHz Microprocessor, " Digest of Technical Papers, VLSI Circuits Symposium, 1995.