Micro-Operation Cache: A power aware frontend for variable instruction length ISA

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 4-9

  Solomon, B ^a   Mendelson, A ^a   Orenstien, D ^a   Almog, Y ^a   Ronen, R ^a  

^a INTEL CORPORATION   (Israel)

Author keywords

Instruction cache; Instruction fetch; Micro operation cache; Power reduction

Indexed keywords

ALGORITHMS; BANDWIDTH; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; ROM;

INSTRUCTION CACHE (IC); INSTRUCTION FETCH;

BUFFER STORAGE;

EID: 0034863487     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. The block-based trace cache
2. Alternative fetch and issue policies for the trace cache fetch mechanism
3. eXtended block cache
4. Pipeline gating: Speculation control for energy reduction
5. Trace cache: A low latency approach to high bandwidth instruction fetching