Guarded evaluation: pushing power management to logic synthesis/design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 10, 1998, Pages 1051-1060

  Tiwari, Vivek ^a   Malik, Sharad ^b   Ashar, Pranav ^a,b  

^a Princeton University   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; OPTIMIZATION;

REGISTER-TRANSFER LEVEL;

LOGIC DESIGN;

EID: 0032183716     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.728924     Document Type: Article

References (16)

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