A first-order superscalar processor model

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn 31, Issue , 2004, Pages 338-349

  Karkhanis, Tejas S ^a   Smith, James E ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA CACHES; MICROARCHITECTURES; SUPERSCALAR PROCESSOR MODELS;

APPROXIMATION THEORY; BUFFER STORAGE; COMPUTER SIMULATION; MATHEMATICAL MODELS; STATISTICS;

PROGRAM PROCESSORS;

EID: 4644299010     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. G. Sohi and S. Vajapeyam, "Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors," International Symposium on Computer Architecture, pp. 27-34, 1987.
2. P. G. Emma and E. S. Davidson, "Characterization of Branch and Data Dependencies on Programs for Evaluating Pipeline performance," IEEE Transactions on Computers, vol. 36, pp. 859-875, 1987.
3. A. Hartstein and T. R. Puzak, "The Optimum Pipeline Depth for a Microprocessor," International Symposium on Computer Architecture, pp. 7-13, 2002.
4. E. Sprangle and D. Carmean, "Increasing Processor Performance by Implementing Deeper Pipelines," International Symposium on Computer Architecture, pp. 25-34, 2002.
5. D. B. Noonburg and J. P. Shen, "Theoretical Modeling of Superscalar Processor Performance," International Symposium on Microarchitecture, pp. 52-62, 1994.
6. P. Michaud, A. Seznec, and S. Jourdan, "Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors," International Symposium on Parallel Architectures and Compilation Techniques, 1999.
7. P. Michaud, A. Seznec, and S. Jourdan, "An Exploration of Instruction Fetch Requirement in Out-Of-Order Superscalar Processors," International Journal of Parallel Programming vol. 29, 2001.
8. S. Nussbaum and J. E. Smith, "Modeling Superscalar Processors via Statistical Simulation," International Symposium on Parallel Architectures and Compilation Techniques, 2001.
9. R. Carl and J. E. Smith, "Modeling Superscalar Processors via Statistical Simulation," Workshop on Performance Analysis and Its Impact on Design, 1998.
10. L. Eeckhout, K. De Bosschere, and H. Neefs, "Performance Analysis Through Synthetic Trace Generation," International Symposium on Performance Analysis of Systems and Software, 2000.
11. D. B. Noonburg and J. P. Shen, "A Framework for Statistical Modeling of Superscalar Processor Performance," International Symposium on High Performance Computer Architecture, pp. 298-309, 1997.
12. D. Sorin, V. Pai, S. V. Adve, M. K. Vernon, and D. A. Wood, "Analytic Evaluation of Shared Memory Systems with ILP Processors," International Symposium on Computer Architecture, pp. 380-391, 1998.
13. B. A. Fields, R. Bodik, M. D. Hill, and C. J. Newburn, "Using Interaction Costs for Microarchitectural Bottleneck Analysis," International Symposium on Microarchitecture, pp. 228-239, 2003.
14. D. J. Ofelt, "Efficient Performance Prediction for Modern Microprocessors," Stanford University PhD Thesis, 1999.
15. E. Riseman and C. Foster, "The Inhibition of Potential Parallelism by Conditional Jumps," IEEE Transactions on Computers, vol. C-21, pp. 1405-1411, 1972.
16. N. P. Jouppi, "The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance," IEEE Transactions on Computers, vol. 38, pp. 1645-1658, 1989.
17. S. R. Kunkel and J. E. Smith, "Optimal pipelining in supercomputers," International Symposium on Computer Architecture, pp. 404-411, 1986.
18. M. S. Hrishikesh, D. Burger, N. P. Jouppi, S. W. Keckler, K. I. Farkas, and P. Shivakumar, "The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays," International Symposium on Computer Architecture, pp. 14-24, 2002.