The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best

IEEE Computer Architecture Letters

Volumn 4, Issue 1, 2005, Pages 1-4

  Sazeides, Yiannakis ^a   Constantinou, Theofanis ^a   Kumar, Rakesh ^b   Tullsen, Dean M ^b  

^a UNIVERSITY OF CYPRUS   (Cyprus)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 85008056730     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2005.2     Document Type: Article

References (6)

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2. D. Brooks, P. Bose, S. Schuster, H. Jacobson, P. Kudva, A. Buyuktosunoglu, J.-D. Wellman, V. V. Zyuban, M. Gupta, and P. W. Cook, “Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors,” IEEE Micro, vol. 20, no. 6, pp. 26–44, November/December 2000.
3. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power Digital CMOS Design,” IEEE Journal of Solid State Circuits, vol. 27, no. 4, pp. 473–484, April 1992.
4. M. Horowitz, T. Indermaur, and R. Gonzalez, “Low Power Digital Design,” in IEEE International Symposium on Low Power Electronics, October 1994, pp. 8–11.
5. R. Kumar, K. Farkas, N. Jouppi, P. Ranganathan, and D. Tullsen, “Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction,” in 36th International Symposium on Microarchitecture, December 2003, pp. 81–92.
6. R. Kumar, K. Farkas, N. Jouppi, P. Ranganathan, and D. Tullsen, “Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures,” Computer Architecture Letters, vol. 2, April 2003.