Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 70-75

  Ghose, Kanad ^a   Kamble, Milind B ^a  

^a BINGHAMTON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; ELECTRIC LOSSES; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE;

BIT-LINE SEGMENTATION; MULTIPLE LINE BUFFERS; SUPERSCALAR PROCESSOR CACHES;

BUFFER STORAGE;

EID: 0033358971     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/313817.313860     Document Type: Article

References (13)