Static energy reduction techniques for microprocessor caches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 3, 2003, Pages 303-313

  Hanson, Heather ^a   Hrishikesh, M S ^a   Agarwal, Vikas ^a   Keckler, Stephen W ^b   Burger, Doug ^b  

^a The University of Texas at Austin   (United States)

^b NONE   (United States)

Author keywords

Dual Vt; Gated Vdd; Leakage current; Low power design; Multithreshold CMOS (MTCMOS); Power consumption model; Static energy

Indexed keywords

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); LEAKAGE CURRENTS; MATHEMATICAL MODELS; SENSITIVITY ANALYSIS;

CACHE LATENCY; LEAKAGE REDUCTION; STATIC ENERGY CONSUMPTION;

MICROPROCESSOR CHIPS;

EID: 0042921418     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.812370     Document Type: Article

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