A first glance at Kilo-instruction based multiprocessors

2004 Computing Frontiers Conference

Volumn , Issue , 2004, Pages 212-221

  Galluzzi, Marco ^a   Beivide, Ramón ^b   Puente, Valentín ^b   Gregorio, José Ángel ^b   Cristal, Adrián ^a   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b UC   (Spain)

Author keywords

CC NUMA; Inflight Instructions; Instruction Window; Kilo instruction Processors; Memory wall; ROB; Shared Memory Multiprocessors

Indexed keywords

ALGORITHMS; CACHE MEMORY; COMPUTER AIDED INSTRUCTION; DATA STORAGE EQUIPMENT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS;

CC-NUMA; INFLIGHT INSTRUCTIONS; INSTRUCTION WINDOWS; KILO-INSTRUCTION PROCESSORS; MEMORY WALLS; ROB; SHARED-MEMORY MULTIPROCESSORS;

MULTIPROCESSING SYSTEMS;

EID: 4143054872     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/977091.977120     Document Type: Conference Paper

References (43)

1. H. Akkary, R. Rajwar, and S. Srinivasan, Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. Proceedings of the 36th Annual ACM/IEEE Intl. Symposium on Microarchitecture, pages 423-434, December 2003.
2. J.-L. Baer and T.-F. Chen. An Effective On-chip Preloading Scheme to Reduce Data Access Penalty. In Proceedings of Supercomputing'91, pages 176-186, November 1991.
3. W. Camp and J. Tomkins. The Red Storm Computer Architecture and its Implementation. Conference on High-Speed Computing, April 2003.
4. C. Carrion, R. Beivide, J. Gregorio, and F. Vallejo. A Flow Control Mechanism to Avoid Message Deadlock in K-ary N-cube Networks. Fourth International Conference on High Performance Computing, pages 322-329, December 1997.
5. R. Chappell, J. Stark, S. Kim, S. Reinhardt, and Y. Patt. Simultaneous Subordinate Microthreading (SSMT). Proceedings of the 26th Annual Intl. Symposium on Computer Architecture, pages 186-195, May 1999.
6. J. D. Collins, D. M. Tullsen, H. Wang, and J. P. Shen. Dynamic Speculative Precomputation. Proceedings of the. 34th Annual ACM/IEEE Intl. Symposium on Microarchitecture, pages 306-317, December 2001.
7. A. Cristal, J. F. Martinez, J. Llosa, and M. Valero. A Case for Resource-conscious Out-of-order Processors. In IEEE TCCA Computer Architecture Letters, 2, October 2003.
8. A. Cristal, D. Ortega, J. Llosa, and M. Valero. Kilo-instruction Processors. Proceedings of the 5th International Symposium on High Performance Computing (invited paper), pages 10-25, October 2003.
9. A. Cristal, D. Ortega, J. Llosa, and M. Valero. Out-of-Order Commit Processors. Proceedings of the 10th Intl. Conference on High Performance Computer Architecture, February 2004.
10. A. Cristal, M. Valero, A. Gonzalez, and J. Llosa. Large Virtual ROBs by Processor Checkpointing. Technical Report UPC-DAC-2002-39, Universidad Politécnica de Cataluña, July 2002.
11. M. Dubois and Y. Song. Assisted Execution. Technical Report CENG 98-25, Department of EE-Systems, University of Southern California, October 1998.
12. M. Galles. Spider: A High-Speed Network Interconnect. IEEE Micro, 17(1):34-39, Jan.-Feb. 1997.
13. K. Gharachorloo, A. Gupta, and H. Hennessy. Hiding Memory Latency Using Dynamic Scheduling in Shared-memory Multiprocessors. Proceedings of the 19th Annual Intl. Symposium on Computer Architecture, pages 22-33, May 1992.
14. K. Gharachorloo, A. Gupta, and J. Hennessy. Performance Evaluation of Memory Consistency Models for Shared-memory Multiprocessors. Proceedings of the 4th Intl. Conference on Architectural Support for Programming Languages and Operating Systems, pages 245-257, April 1991.
15. C. Gniady, B. Falsafi, and T. Vijaykumar. Is SC + ILP = RC? Proceedings of the 26th Annual Intl. Symposium on Computer Architecture, pages 162-171, May 1999.
16. J. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, San Mateo, California, 3rd edition, 2003.
17. W. Hwu and Y. Patt. Checkpoint Repair for Out-of-Order Execution Machines, pages 18-26, December 1987.
18. D. Joseph and D. Grunwald. Prefetching Using Markov Predictors. Proceedings of the 24th Annual Intl. Symposium on Computer Architecture, pages 252-263, June 1997.
19. T. Karkhanis and J. Smith. A Day in the Life of a Cache Miss. 2nd Annual Workshop on Memory Performance Issues (WMPI), June 2002.
20. M. Karlsson, F. Dahlgren, and P. Stenstrom. A Prefetching Technique for Irregular Accesses to Linked Data Structures. Proceedings of the 6th Intl. Conference on High Performance Computer Architecture, pages 206-217, January 2000.
21. A. Klaiber and H. Levy. An Architecture for Software-Controlled Data Prefetching. Proceedings of the 18th Annual Intl. Symposium on Computer Architecture, pages 43-53, May 1991.
22. J. Martinez, A. Cristal, M. Valero, and J. Llosa. Ephemeral Registers. Technical Report CSL-TR-2003-1035, Cornell Computer Systems Lab, 2003.
23. T. Monreal, A. Gonzalez, M. Valero, J. Gonzalez, and V. Vinals. Delaying Physical Register Allocation Through Virtual-Physical Registers. Proceedings of the Send Annual ACM/IEEE Intl. Symposium on Microarchitecture, pages 186-192, November 1999.
24. T. Mowry, M. Lam, and A. Gupta. Design and Evaluation of a Compiler Algorithm for Prefetching. Proceedings of the 5th Intl. Conference on Architectural Support for Programming Languages and Operating Systems, pages 62-73, October 1992.
25. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb. The Alpha 21364 Network Architecture. In Proceedings of Hot Interconnects 9, August 2001.
26. N.R. Adiga et al. An Overview of the BlueGene/L Supercomputer. In Proceedings of Supercomputing'02, November 2002.
27. D. Ortega, E. Ayguade, J.-L. Baer, and M. Valero. Cost-Effective Compiler Directed Memory Prefetching and Bypassing. Proceedings of the 11th Intl. Conference on Parallel Architectures and Compilation Techniques, pages 189-198, September 2002.
28. V. Pai, P. Ranganathan, and S. Adve. RSIM: An execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors. IEEE TCCA Newsletter, 35(11):37-48, October 1997.
29. I. Park, C. Ooi, and T. Vijaykumar. Reducing Design Complexity of the Load/Store Queue. Proceedings of the 36th Annual ACM/IEEE Intl. Symposium on Microarchitecture, pages 411-422, December 2003.
30. V. Puente, J. Gregorio, and R. Beivide. SICOSYS: An Integrated Framework for Studying Interconnection Networks in Multiprocessor Systems. Proceedings of the 10th Euromicro Workshop on Parallel and Distributed Processing, pages 360-368, January 2002.
31. V. Puente, J. Gregorio, R. Beivide, and C. Izu. On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors. IEEE Transactions on Parallel and Distributed Systems, 14(5), May 2003.
32. V. Puente, C. Izu, J. Gregorio, R. Beivide, and F. Vallejo. The Adaptive Bubble Router. Journal on Parallel and Distributed Computing, 61(9):1180-1208, September 2001.
33. P. Ranganathan, V. Pai, and S. Adve. Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models. In Proceedings of the 9th Symposium on Parallel Algorithms and Architectures, June 1997.
34. A. Roth and G. S. Sohi. Speculative Data-Driven Multithreading. Proceedings of the 7th Intl. Conference on High Performance Computer Architecture, pages 37-50, January 2001.
35. S. Sethumadhavan, R. Desikan, D. Burger, C. Moore, and S. Keckler. Scalable Hardware Memory Disambiguation for High ILP Processors. Proceedings of the 36th Annual ACM/IEEE Intl. Symposium on Microarchitecture, pages 399-410, December 2003.
36. J. Singh, W. Weber, and A. Gupta. SPLASH: Stanford Parallel Applications for Shared-Memory. Computer Architecture News, 20(1):5-44, March 1992.
37. A. Smith. Cache Memories. Computing surveys, 14(3):473-530, September 1982.
38. Y. Sohilin, J. Lee, and J. Torrellas. Using a User-Level Memory Thread for Correlation Prefetching. Proceedings of the 29th Annual Intl. Symposium on Computer Architecture, pages 171-182, May 2002.
39. C. Stunkel, J. Herring, B. Abali, and R. Sivaram. A New Switch Chip for IBM RS/6000 SP Systems. In Proceedings of Supercomputing'99, November 1999.
40. R. Tomasulo. An Efficient Algorithm for Exploiting' Multiple Arithmetic Units. IBM Journal of Research and Development, (11):25-33, January 1967.
41. S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. Proceedings of the Send Annual Intl. Symposium on Computer Architecture, pages 24-36, June 1995.
42. W. Wulf and S. McKee. Hitting the Memory Wall: Implications of the Obvious. Computer Architecture News, 23(1):20-24, March 1995.
43. C. Zilles and G. Sohi. Execution-based Prediction using Speculative Slices. Proceedings of the 28th Annual Intl. Symposium on Computer Architecture, pages 2-13, July 2001.