The alpha 21264 microprocessor

IEEE Micro

Volumn 19, Issue 2, 1999, Pages 24-36

  Kessler, R E ^a,b,c  

^a HEWLETT PACKARD COMPANY   (United States)

^b ACM   (United States)

^c IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DATA FLOW ANALYSIS; DIGITAL ARITHMETIC; INTERFACES (COMPUTER); PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; QUEUEING NETWORKS; RANDOM ACCESS STORAGE; TIMING CIRCUITS;

BUS INTERFACE UNITS (BIU); LOAD QUEUE (LDQ); MISS ADDRESS FILES (MAF); STORE QUEUE (SRQ);

MICROPROCESSOR CHIPS;

EID: 0032639289     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.755465     Document Type: Article

References (9)

1. D. Dobberpuhl et al., "A 200 MHz 64-bit Dual Issue CMOS Microprocessor," IEEE J. Solid State Circuits, Vol. 27, No. 11, Nov. 1992, pp. 1,555-1,567.
2. J. Edmondson et al., "Superscalar Instruction Execution in the 21164 Alpha Microprocessor," IEEE Micro, Vol. 15, No. 2, Apr. 1995; pp. 33-43.
3. B. Gieseke et al., "A 600 MHz Superscalar RISC Microprocessor with Out-of-Order Execution," IEEE Int'l Solid-State Circuits Conf. Dig., Tech. Papers, IEEE Press, Piscataway, N.J., Feb. 1997, pp. 176-177.
4. D. Leibholz and R. Razdan, "The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor," Proc. IEEE Compcon 97, IEEE Computer Soc. Press, Los Alamitos, Calif., 1997, pp. 28-36.
5. R.E. Kessler, E.J. McLellan, and D.A. Webb, "The Alpha 21264 Microprocessor Architecture," Proc. 1998 IEEE Int Conf. Computer Design: VLSI in Computers and Processors, IEEE Computer Soc. Press, Oct. 1998, pp. 90-95.
6. M. Matson et al., "Circuit Implementation of a 600 MHz Superscalar RISC Microprocessor," 1998 IEEE Int'l Conf. Computer Design: VLSI in Computers and Processors, Oct. 1998, pp. 104-110.
7. J.D. McCalpin, "STREAM: Sustainable Memory Bandwidth in High-Performance Computers," Univ. of Virginia, Dept. of Computer Science, Charlottesville, Va.; http://www.cs.virginia.edu/stream/.
8. S. McFarling, Combining Branch Predictors, Tech. Note TN-36, Compaq Computer Corp. Western Research Laboratory, Palo Alto, Calif., June 1993; http://www.research. digital.com/wrl/techreports/abstracts/ TN-36.html.
9. T. Fischer and D. Leibholz, "Design Tradeoffs in Stall-Control Circuits for 600 MHz Instruction Queues," Proc. IEEE Int'l Solid-State Circuits Conf. Dig., Tech. Papers, IEEE Press, Feb. 1998, pp. 398-399.