Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 480-485

  Anis, Mohab ^a   Areibi, Shawki ^b   Mahmoud, Mohamed ^a   Elmasry, Mohamed ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

^b UNIVERSITY OF GUELPH   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

GATE-CLUSTERING TECHNIQUES;

BENCHMARKING; ELECTRIC LOSSES; LEAKAGE CURRENTS; VLSI CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0036049095     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012673     Document Type: Article

References (7)

1. Design and optimization of dual-threshold circuits for low-voltage low-power applications
2. Stand-by power minimization through simulataneous threshold voltage selection and circuit sizing
3. 1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS
4. MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
5. Transistor sizing issues and tool for multi-threshold CMOS technology
6. Technology for advanced high-performance microprocessors