Trace cache: A low latency approach to high bandwidth instruction fetching

Proceedings of the Annual International Symposium on Microarchitecture

Volumn , Issue , 1996, Pages 24-34

  Rotenberg, Eric ^a   Bennett, Steve ^a   Smith, James E ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; MICROCOMPUTERS;

HIGH BANDWIDTH INSTRUCTION FETCHING; INSTRUCTION BENCHMARK SUITE (IBS); TRACE CACHE;

BUFFER STORAGE;

EID: 0030380559     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)