Effectiveness and scaling trends of leakage control techniques for sub-130 nm CMOS technologies

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 122-127

  Chatterjee, B ^a   Sachdev, M ^a   Hsu, S ^b   Krishnamurthy, R ^b   Borkar, S ^b  

^a UNIVERSITY OF WATERLOO   (Canada)

^b INTEL CORPORATION   (United States)

Author keywords

CMOS technology; Computational modeling; Degradation; Delay; Driver circuits; Leakage current; Microprocessors; Permission; Radio frequency; Threshold voltage

Indexed keywords

DEGRADATION; DELAY CIRCUITS; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; POWER ELECTRONICS; THRESHOLD VOLTAGE;

CMOS TECHNOLOGY; COMPUTATIONAL MODEL; DELAY; DRIVER CIRCUIT; PERMISSION; RADIO FREQUENCIES;

CMOS INTEGRATED CIRCUITS;

EID: 1542359161     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231847     Document Type: Conference Paper

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