Compiler-directed instruction cache leakage optimization

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2002-January, Issue , 2002, Pages 208-218

  Zhang, W ^a   Hu, J S ^a   Degalahal, V ^a   Kandemir, M ^a   Vijaykrishnan, N ^a   Irwin, M J ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Cache memory; Counting circuits; Energy consumption; Hip; Impedance; Leak detection; Microprocessors; Optimizing compilers; Threshold voltage; Voltage control

Indexed keywords

BUDGET CONTROL; BUFFER STORAGE; COMPUTER ARCHITECTURE; COUNTING CIRCUITS; ELECTRIC IMPEDANCE; ENERGY UTILIZATION; HOT ISOSTATIC PRESSING; LEAK DETECTION; MICROPROCESSOR CHIPS; PROGRAM COMPILERS; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

CONSERVATIVE APPROACHES; INSTRUCTION CACHES; LEAKAGE CONTROL; LEAKAGE ENERGIES; LEAKAGE OPTIMIZATION; OPTIMISTIC APPROACH; OPTIMIZING COMPILERS; POWER CONSUMED;

CACHE MEMORY;

EID: 84948993747     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2002.1176251     Document Type: Conference Paper

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