Access-mode predictions for low-power cache design

IEEE Micro

Volumn 22, Issue 2, 2002, Pages 58-71

  Zhu, Zhichun ^a   Zhang, Xiaodong ^a  

^a Dept of Economics and Thomas Jefferson Program in Public Policy at the College of William and Mary   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER WORKSTATIONS; ENERGY CONSERVATION; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; SHIFT REGISTERS;

ACCESS MODE PREDICTION; CACHE DESIGN; MULTICOLUMN CACHE; SET ASSOCIATIVE CACHE; WAY PREDICTION;

CACHE MEMORY;

EID: 0036504804     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2002.997880     Document Type: Article

References (19)

1. Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors
2. Alpha processors: A history of power issues and a look to the future
3. Cache design trade-offs for power and performance optimization: A case study
4. Selective cache ways: On-demand cache resource allocation
5. Exploiting choices in resizable cache design to optimize deep-submicron processor energy-delay
6. SH3: High code density, low-power
7. Way-predicting set-associative cache for high performance and low energy consumption
8. A modified approach to data cache management
9. Speculation techniques for improving load related instruction scheduling
10. Reducing set-associative cache energy via way-prediction and selective direct-mapping
11. L1 data cache decomosition for energy efficiency
12. A study of branch prediction strategies
13. Alternative implementations of two-level adaptive branch prediction
14. Improving the accuracy of dynamic branch prediction using branch correlation
15. Two fast and high-associativity cache schemes
16. Multiple access caches: Energy implications