Reducing power density through activity migration

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 217-222

  Heo, Seongmoo ^a   Barr, K ^a   Asanovic K ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Integrated circuit modeling; Integrated circuit reliability; Laboratories; Microprocessors; Packaging; Permission; Power dissipation; Power system modeling; Temperature dependence; Thermal management

Indexed keywords

ENERGY DISSIPATION; INTEGRATED CIRCUITS; LABORATORIES; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; PACKAGING; POWER ELECTRONICS; TEMPERATURE; TEMPERATURE CONTROL; TEMPERATURE DISTRIBUTION;

INTEGRATED CIRCUIT MODELING; INTEGRATED CIRCUIT RELIABILITY; PERMISSION; POWER SYSTEM MODEL; TEMPERATURE DEPENDENCE;

ELECTRIC LOSSES;

EID: 1542269347     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231865     Document Type: Conference Paper

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