AltiVec extension to PowerPC accelerates media processing

IEEE Micro

Volumn 20, Issue 2, 2000, Pages 85-95

  Diefendorff, Keith ^a,c,e,f   Dubey, Pradeep K ^b,f,g,h,i,j   Hochsprung, Ron ^c,f,k,l   Scales, Hunter ^d,m,n  

^a Microprocessor Report ^*

^b IBM RESEARCH   (United States)

^c APPLE INC   (United States)

^d MOTOROLA INC   (United States)

^e UNIVERSITY OF AKRON   (United States)

^f IEEE

^g IBM INDIA RESEARCH LAB   (India)

^h BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE   (India)

ⁱ UNIVERSITY OF MASSACHUSETTS   (United States)

^j PURDUE UNIVERSITY   (United States)

^k PowerPC Arch Development Team

^l ILLINOIS INSTITUTE OF TECHNOLOGY   (United States)

^m Austin University   (United States)

ⁿ Cahners MicroDesign Resources   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

SINGLE INSTRUCTION MULTIPLE DATA (SIMD) PARALLELISM; SOFTWARE-DIRECTED PREFETCH STREAMS; VECTOR DOT PRODUCT;

COMPUTER SYSTEMS PROGRAMMING; DATA STRUCTURES; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; PARALLEL PROCESSING SYSTEMS; PERSONAL COMPUTERS; PIPELINE PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); THREE DIMENSIONAL COMPUTER GRAPHICS; WAVELET TRANSFORMS;

COMPUTER ARCHITECTURE;

EID: 0033872689     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.848475     Document Type: Article

References (13)

1. A. Peleg and U. Weiser, "MMX Technology Extension to the Intel Architecture," IEEE Micro, July/Aug. 1996, pp. 42-50.
2. K. Diefendorff, "Katmai Enhances MMX," Microprocessor Report, Oct. 5, 1998, pp 1, 6-9.
3. M. Tremblay et al., "VIS Speeds New Media Processing," IEEE Micro. July/Aug. 1996, pp. 10-20.
4. R.B. Lee, "Subword Parallelism with MAX-2," IEEE Micro, July/Aug. 1996, pp. 51-59.
5. "MIPS Digital Media Extension," Instruction Set Architecture Specification, http://www. mips.com/MDMXspec.ps (Oct. 21, 1997).
6. "AltiVec Extension to PowerPC," Instruction Set Architecture Specification, http://www. motorola.com/AltiVec (May 7, 1998).
7. M. Phillip et al., "AltiVec Technology: Accelerating Media Processing Across the Spectrum," Proc. Hot Chips 10, 1998, available at http://www.hotchips.org.
8. K. Diefendorff and P. Dubey, "How Multimedia Workloads Will Change Processor Design," Computer. Sept. 1997, pp. 43-4.
9. ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, IEEE Press, Piscataway, N.J.
10. E.R. Berlekamp, Algebraic Coding Theory, Aegean Park Press, Laguna Hills, Calif., 1984.
11. I. Pitas, Digital Image Processing Algorithms, Prentice Hall, New York, 1993.
12. C. Abbott et al., "Broadband Algorithms with the MicroUnity MediaProcessor," Proc. Compcon 96, IEEE Computer Soc. Press, Los Alamitos, Calif., 1996, pp. 349-354
13. C. Hansen, "MicroUnity's MediaProcessor Architecture," IEEE Micro, July/Aug. 1996, pp. 34-41.