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Volumn , Issue , 2002, Pages 48-51

Low-leakage asymmetric-cell SRAM

Author keywords

Dual Vt; Low leakage; Low power; SRAM

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; THRESHOLD VOLTAGE; TRANSISTORS;

EID: 0036949087     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146707     Document Type: Conference Paper
Times cited : (60)

References (8)
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    • S. Borkar, "Design challenges of technology scaling," IEEE MICRO, vol. 19, no.4, pp. 23-29, July-Aug. 1999.
    • (1999) IEEE MICRO , vol.19 , Issue.4 , pp. 23-29
    • Borkar, S.1
  • 2
    • 0034428063 scopus 로고    scopus 로고
    • EDA challenges facing future microprocessor design
    • Dec.
    • T. Kam et. al., "EDA challenges facing future microprocessor design," in IEEE Transactions on Computer-Aided Design, vol. 19. no. 12, Dec. 2000.
    • (2000) IEEE Transactions on Computer-Aided Design , vol.19 , Issue.12
    • Kam, T.1
  • 3
    • 0033645907 scopus 로고    scopus 로고
    • Dual-Vt SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13um technology generation
    • F. Hamzaoglu et. al., "Dual-Vt SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13um technology generation," in Proc. 2000 Intl. Symp. on Low Power Electronics and Design, July 2000.
    • Proc. 2000 Intl. Symp. on Low Power Electronics and Design, July 2000
    • Hamzaoglu, F.1
  • 5
    • 0012528715 scopus 로고    scopus 로고
    • Asymmetric-cell caches: Exploiting bit value biases to reduce leakage power in deep-submicron, high-performance caches
    • Univ. of Toronto
    • N. Azizi, A. Moshovos, F. N. Najm, B. Falsafi, "Asymmetric-cell caches: exploiting bit value biases to reduce leakage power in deep-submicron, high-performance caches," ECE Computer Group Technical Report TR-01-01-02, Univ. of Toronto.
    • ECE Computer Group Technical Report TR-01-01-02
    • Azizi, N.1    Moshovos, A.2    Najm, F.N.3    Falsafi, B.4
  • 6
    • 0023437909 scopus 로고
    • Static-noise margin analysis of MOS SRAM cells
    • Oct.
    • E. Seevinck Sr et. al., "Static-noise margin analysis of MOS SRAM cells," IEEE Journal of Solid-State Circuits, vol. 22, pp. 748-754, Oct. 1987.
    • (1987) IEEE Journal of Solid-State Circuits , vol.22 , pp. 748-754
    • Seevinck E., Sr.1
  • 8
    • 0035308547 scopus 로고    scopus 로고
    • The impact of intrinsic device fluctuations on CMOS SRAM cell stability
    • Apr.
    • A. Bhavnagarwala et. al., "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," in IEEE J. of Solid-State Circuits, vol. 36, Apr. 2001.
    • (2001) IEEE J. of Solid-State Circuits , vol.36
    • Bhavnagarwala, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.