Impact of scaling on the effectiveness of dynamic power reduction schemes

Proceedings-IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 382-387

  Duarte, D ^a,b   Vijaykrishnan, N ^b   Irwin, M J ^b   Kim, H S ^b   McFarland, G ^a  

^a INTEL CORPORATION   (United States)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER ARCHITECTURE; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; SHORT CIRCUIT CURRENTS; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

DYNAMIC POWER REDUCTION; ENERGY REDUCTION; MICRO-ARCHITECTURAL CHANGE; VOLTAGE SCALING;

VLSI CIRCUITS;

EID: 0036396948     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2002.1106798     Document Type: Article

References (11)

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