High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2000, Pages 227-232

  Sirisantana, Naran ^a   Wei, Liqiong ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; DOPING (ADDITIVES); ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; POWER INTEGRATED CIRCUITS; SWITCHING CIRCUITS; THRESHOLD VOLTAGE;

MULTIPLE CHANNEL LENGTH; MULTIPLE OXIDE THICKNESS;

CMOS INTEGRATED CIRCUITS;

EID: 0033680440     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)