An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2002, Pages 211-222

  Kim, Changkyu ^a   Burger, Doug ^a   Keckler, Stephen W ^a  

^a The University of Texas at Austin ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; DATA TRANSFER; EVALUATION; PERFORMANCE; RESPONSE TIME (COMPUTER SYSTEMS); STORAGE ALLOCATION (COMPUTER); COMPUTER OPERATING SYSTEMS; LINGUISTICS; NANOTECHNOLOGY; WIRE;

CACHE ACCESS TIMES; NON-UNIFORM CACHE ARCHITECTURES; SOFTWARE PACKAGE CACTI; SOFTWARE PACKAGE HSPICE; ACCESS TIME; CACHE ACCESS; CACHE ARCHITECTURE; CACHE DESIGN; CACHE HIERARCHIES; CACHE STRUCTURE; NON-UNIFORM CACHE ARCHITECTURE; NONUNIFORM; NONUNIFORMITY; ON CHIP COMMUNICATION; ON-CHIP CACHE; PHYSICAL DESIGN; PHYSICAL LOCATIONS; SILICON AREA; THREE-LEVEL; WIRE DELAYS;

COMPUTER ARCHITECTURE; DESIGN;

EID: 0036949388     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/605397.605420     Document Type: Conference Paper

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