Leakage energy management in cache hierarchies

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2002-January, Issue , 2002, Pages 131-140

  Li, L ^a   Kadayif, I ^a   Tsai, Y F ^a   Vijaykrishnan, N ^a   Kandemir, M ^a   Irwin, M J ^a   Sivasubramaniam, A ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Cache memory; Energy capture; Energy consumption; Energy management; Engineering profession; Integrated circuit technology; Power generation; Power supplies; Threshold voltage; Turning

Indexed keywords

BUDGET CONTROL; BUFFER STORAGE; EMBEDDED SYSTEMS; ENERGY MANAGEMENT; ENERGY UTILIZATION; MEMORY ARCHITECTURE; PARALLEL ARCHITECTURES; POWER GENERATION; PROFESSIONAL ASPECTS; THRESHOLD VOLTAGE; TURNING;

CACHE HIERARCHIES; CYCLE-ACCURATE SIMULATION; ENERGY CAPTURE; ENERGY OPTIMIZATION; ENGINEERING PROFESSION; HIGH PERFORMANCE ARCHITECTURES; INTEGRATED CIRCUIT TECHNOLOGY; POWER SUPPLY;

CACHE MEMORY;

EID: 84948762407     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2002.1106012     Document Type: Conference Paper

References (20)

1. Berkeley predictive model http://www-device.eecs.berkeley.edu.
2. D. H. Albonesi. Selective cache ways: on demand cache resource allocation. In MICRO-32, pp. 248-259, Nov. 1999.
3. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In ISCA-27, June 2000.
4. D. C. Burger and T. M. Austin. The SimpleScalar tool-set, Version 2.0. Technical Report 1342, Dept. of Computer Science, UW, June 1997.
5. A. Chandrakasan, W. J. Bowhill, and F. Fox. Design of High-Performance Microprocessor Circuits. IEEE Press, 2001.
6. G. Chen, R. Shetty, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and M. Wolczko. Tuning garbage collection in an embedded java environment. In HPCA-8, Feb. 2002.
7. K. Flautner, N. Kim, S. Martin, D. Blaauw, and T. Mudge. Drowsy caches: Simple techniques for reducing leakage power. In ISCA-29, May 2002.
8. S. Heo, K. Barr, M. Hampton, and K. Asanovic. Dynamic fine-grain leakage reduction using leakage-biased bitlines. In ISCA-29, May 2002.
9. K. Itoh, K. Sasaki, and Y. Nakagome. Trends in low-power RAM circuit technologies. Proceedings of IEEE, 83(4):524-543, Apr. 1995.
10. N. Jouppi and S. Wilton. Tradeoffs in two-level on-chip caching. In ISCA-21, pp. 34-45. IEEE Computer Society Press, 1994.
11. H. Kawaguchi, K. Nose, and T. Sakurai. A super cutoff CMOS scheme for 0.5V supply voltage with picoampere standby current. Journal of Solid-State Circuits, 35(10):1498-1501, Oct. 2000.
12. S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: exploiting generational behavior to reduce cache leakage power. In ISCA-28, June 2001.
13. C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. In MICRO-30, pp. 330-335, Dec. 1997.
14. T. May and M. Woods. Alpha-particled-induced soft errors in dynamic memories. IEEE Trans. on Electron Devices, ED-26(1), Jan. 1979.
15. P. R. V. d. Meer and A. V. Staveren. Standby-current reduction for deep sub-micron VLSI CMOS circuits: smart series switch. In the ProRISC/IEEE Workshop, pp. 401-404, Dec. 2000.
16. B. Nikolic. State-preserving leakage control mechanisms. Gigascale Silicon Research Center Annual Report, Sept. 2001.
17. J. Rabaey. Digital integrated circuits: a design perspective. Prentice Hall Inc. online revisions of new chapters. http://bwrc.eecs.berkeley.edu/Classes/ICDesign/EE141f00/notes.html.
18. L. Villa, M. Zhang, and K. Asanovic. Dynamic zero compression for cache energy reduction. In MICRO-33, Dec. 2000.
19. S. Yang, M. D. Powell, B. Falsafi, K. Roy, and T. N. Vijaykumar. An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches. In HPCA-7, Jan. 2001.
20. H. Zhou, M. C. Toburen, E. Rotenberg, and T. M. Conte. Adaptive mode control: A static-power-efficient cache design. In International Conference on Parallel Architectures and Compilation Techniques (PACT'01), Sept. 2001.