Single-VDD and single-VT super-drowsy techniques for low-leakage high-performance instruction caches

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 54-57

  Kim, Nam Sung ^a   Flautner, Krisztián ^b   Blaauw, David ^c   Mudge, Trevor ^c  

^a INTEL CORPORATION   (United States)

^b ARM LTD   (United Kingdom)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Leakage current; Low power

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ENERGY UTILIZATION; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; SIGNAL PROCESSING; TRANSISTORS;

CACHE CIRCUITS; CONTENT ADDRESSABLE MEMORY (CAM); LOW POWER; MEMORY CIRCUITS;

LEAKAGE CURRENTS;

EID: 16244419042     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013254     Document Type: Conference Paper

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