Deterministic clock gating for microprocessor power reduction

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 12, Issue , 2003, Pages 113-122

  Li, Hai ^a   Bhunia, S ^a   Chen, Y ^a   Vijaykumar, T N ^a   Roy, K ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Circuits; Clocks; Decoding; Latches; Microprocessors; Out of order; Performance loss; Pipelines; Power dissipation; Power system reliability

Indexed keywords

BUS DRIVERS; CLOCKS; COMPUTER ARCHITECTURE; DECODING; ENERGY DISSIPATION; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); PIPELINE PROCESSING SYSTEMS; PIPELINES; RECONFIGURABLE HARDWARE; SUPERCOMPUTERS;

EXECUTION UNITS; INSTRUCTION LEVEL PARALLELISM; MICROPROCESSOR DESIGNS; OUT OF ORDER; PERFORMANCE LOSS; POWER REDUCTIONS; POWER SYSTEM RELIABILITY; SUPERSCALAR PROCESSOR;

ELECTRIC LOSSES;

EID: 27944465327     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2003.1183529     Document Type: Conference Paper

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