Power and performance evaluation of globally asynchronous locally synchronous processors

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2002, Pages 158-168

  Iyer, Anoop ^a   Marculescu, Diana ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT LAYOUT; SYNCHRONIZATION; TIMING CIRCUITS;

GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS (GALS) PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0036294823     PISSN: 08847495     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCA.2002.1003573     Document Type: Article

References (19)

1. Micropipelines
2. AMULET3: A 100 MIPS asynchronous embedded processor
3. A low-latency FIFO for mixed-clock systems
4. Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
5. Lower power consumption in clock by using globally asynchronous locally synchronous design style
6. Practical design of globally asynchronous locally synchronous systems
7. Self calibrating clocks for globally asynchronous locally synchronous circuits
8. Pausible clocking-based heterogeneous systems
9. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
10. A clock distribution network for microprocessors
11. Clocking design and analysis for a 600-MHz alpha microprocessor
12. Clock generation and distribution for the first IA-64 microprocessor
13. Performance and Vdd scaling in deep submicrometer CMOS
14. Wattch: A framework for architectural-level power analysis and optimizations
15. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems