Energy-effective issue logic

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2001, Pages 230-239

  Folegnani, D ^a   Gonzalez A ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Adaptive hardware; Energy consumption; Issue logic; Low power

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER SIMULATION; ESTIMATION; PERSONAL COMPUTERS; QUEUEING THEORY;

ARCHITECTURAL POWER EVALUATION; POWER CONSUMPTION ESTIMATION TECHNIQUE; SUPERSCALAR PROCESSOR; WAKE-UP LOGIC;

ELECTRIC POWER UTILIZATION;

EID: 0034838829     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/379240.379266     Document Type: Conference Paper

References (37)

1. Power and performance trade-offs using various caching strategies
2. Dynamic IPC/clock rate optimization
3. The inherent energy efficiency of complexity-adaptive processors
4. "The simplescalar tool set", version 3.0
5. Adaptive thermal management for high-performance microprocessors
6. Wattch: A framework for architectural-level power analysis and optimizations
7. Architectural level power/performance optimization and dynamic power estimation
8. Very low power pipelines using significance compression
9. Instruction scheduling for low power dissipation in high performance microprocessors
10. Reducing the energy of address and data buses with the working-zone encoding technique and its effect on multimedia applications
11. How multimedia workloads will change processor design
12. Reducing power consumption of the issue logic
13. Energy dissipation in general purpose microprocessors
14. The filter cache: An energy efficient memory structure
15. Analytical energy dissipation models for low power caches
16. Pipeline gating: Speculation control for energy reduction
17. Profile-driven code execution for low power dissipation
18. Complexity effective superscalar processors
19. Reducing instruction cache energy using gated wordlines
20. Thermal management system for high performance powerPC microprocessors
21. SPARC64 5: A high performance and high reliability 64-bit SPARC processor
22. Power challenges in the internet world
23. Shrinking devices put the squeeze on system packaging
24. Cache designs for energy efficiency
25. A unified energy estimation framework with integrated hardware-software optimizations
26. Limits of instruction-level parallelism
27. Alpha processors: A history of power issues and a look to the future
28. Inherently lower-power high performance superscalar architectures
29. Energy-driven hardware-software optimizations using simplepower