Temperature-aware microarchitecture

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2003, Pages 2-13

  Skadron, Kevin ^a   Stan, Mircea R ^a   Huang, Wei ^a   Velusamy, Sivakumar ^a   Sankaranarayanan, Karthik ^a   Tarjan, David ^a  

^a University of Virginia   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRONICS PACKAGING; EQUIVALENT CIRCUITS; FINITE ELEMENT METHOD; HEAT RESISTANCE; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; RESPONSE TIME (COMPUTER SYSTEMS); TEMPERATURE CONTROL;

DYNAMIC THERMAL MANAGEMENT; MICROARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 0038684860     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/859619.859620     Document Type: Conference Paper

References (30)

1. A. Bakker and J. Huijsing. High-Accuracy CMOS Smart Temperature Sensors. Kluwer Academic, Boston, 2000.
2. P. Bannon. Personal communication, Sep. 2002.
3. S. Borkar. Design challenges of technology scaling. IEEE Micro, pp. 23-29, Jul.-Aug. 1999.
4. D. Brooks and M. Martonosi. Dynamic thermal management for high-performance microprocessors. In Proc. HPCA-7, pp. 171-82, Jan. 2001.
5. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proc. ISCA-27, pp. 83-94, June 2000.
6. D. C. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. ACM SIGARCH CAN, 25(3): 13-25, June 1997.
7. R. Canal, J.-M. Parcerisa, and A. González. A cost-effective clustered architecture. In Proc. PACT, pp. 160-86, Oct. 1999.
8. Compaq 21364 die photo. From website: CPU Info Center. http://bwrc.eecs.berkeley.edu/CIC/die_photos.
9. A. Dhodapkar, C. H. Lim, G. Cai, and W. R. Daasch. TEM-PEST: A thermal enabled multi-model power/performance estimator. In Proc. PACS, Nov. 2000.
10. M. Fleischmann. Crusoe power management: Cutting x86 operating power through LongRun. In Embedded Processor Forum, June 2000.
11. J. Garrett and M. R. Stan. Active threshold compensation circuit for improved performance in cooled CMOS systems. In Proc. ISCAS, May 2001.
12. S. Gunther, F. Binns, D. M. Carmean, and J. C. Hall. Managing the impact of increasing microprocessor power consumption. Intel Tech. J., Q1 2001.
13. W. Huang, J. Renau, S.-M. Yoo, and J. Torellas. A framework for dynamic energy efficiency and temperature management. In Proc. Micro-33, pp. 202-13, Dec. 2000.
14. A. Krum. Thermal management. In F. Kreith, editor, The CRC handbook of thermal engineering, pp. 2.1-2.92. CRC Press, Boca Raton, FL, 2000.
15. S. Lee, S. Song, V. Au, and K. Moran. Constricting/spreading resistance model for electronics packaging. In Proc. AJTEC, pp. 199-206, Mar. 1995.
16. C.-H. Lim, W. Daasch, and G. Cai. A thermal-aware superscalar microprocessor. In Proc. ISQED, pp. 517-22, Mar. 2002.
17. R. Mahajan. Thermal management of CPUs: A perspective on trends, needs and opportunities, Oct. 2002. Keynote presentation, THERMINIC-8.
18. S. Manne, A. Klauser, and D. Grunwald. Pipeline gating: speculation control for energy reduction. In Proc. ISCA-25, June 1998.
19. J. M. Rabaey. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, Englewood Cliffs, NJ, 1995.
20. E. Rohou and M. Smith. Dynamically managing processor temperature and power. In Proc. FDDO-2, Nov. 1999.
21. M.-N. Sabry. Dynamic compact thermal models: An overview of current and potential advances. In Proc. THERMINIC-8, Oct. 2002.
22. H. Sanchez et al. Thermal management system for high-performance PowerPC microprocessors. In Proc. COMPCON, page 325, 1997.
23. G. Semeraro et al. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling. In Proc. HPCA-8, pp. 29-40, Feb. 2002.
24. T. Sherwood, E. Perelman, and B. Calder. Basic block distribution analysis to find periodic behavior and simulation points in applications. In Proc. PACT, Sept. 2001.
25. SIA. International Technology Roadmap for Semiconductors, 2001.
26. K. Skadron, T. Abdelzaher, and M. R. Stan. Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management. In Proc. HPCA-8, pp. 17-28, Feb. 2002.
27. K. Skadron et al. Temperature-aware microarchitecture: Extended discussion and results. Tech. Report CS-2003-08, U. Va. Dept. of Computer Science, Apr. 2003.
28. S. Velusamy, K. Sankaranarayanan, D. Parikh, T. Abdelzaher, and K. Skadron. Adaptive cache decay using formal feedback control. In Proc. WMPI-2, May 2002.
29. R. Viswanath, W. Vijay, A. Watwe, and V. Lebonheur. Thermal performance challenges from silicon to systems. Intel Tech. J., Q3 2000.
30. Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan. Hotleakage: A temperature-aware model of sub-threshold and gate leakage for architects. Tech. Report CS-2003-05, U. Va. Dept. of Computer Science, Mar. 2003.