-
1
-
-
0036396948
-
Impact of scaling on the effectiveness of dynamic power reduction schemes
-
Sep.
-
D. Duarte, N. Vijaykrishnan, M. J. Irwin, H.-S. Kim, and G. McFarland, "Impact of scaling on the effectiveness of dynamic power reduction schemes," in Proc. Int. Conf. Computer Design, Sep. 2002, pp. 382-387.
-
(2002)
Proc. Int. Conf. Computer Design
, pp. 382-387
-
-
Duarte, D.1
Vijaykrishnan, N.2
Irwin, M.J.3
Kim, H.-S.4
McFarland, G.5
-
2
-
-
0029488569
-
A scheduling model for reduced CPU energy
-
Oct.
-
F. Yao, A. Demers, and S. Shenker, "A scheduling model for reduced CPU energy," in Proc. Symp. Foundations Computer Science, Oct. 1995, pp. 374-382.
-
(1995)
Proc. Symp. Foundations Computer Science
, pp. 374-382
-
-
Yao, F.1
Demers, A.2
Shenker, S.3
-
4
-
-
84949801414
-
LEneS: Task scheduling for low-energy systems using variable supply voltage processors
-
Jan.
-
F. Gruian and K. Kuchcinski, "LEneS: task scheduling for low-energy systems using variable supply voltage processors," in Proc. Conf. Asian South Pacific Design Automation, Jan. 2001, pp. 449-455.
-
(2001)
Proc. Conf. Asian South Pacific Design Automation
, pp. 449-455
-
-
Gruian, F.1
Kuchcinski, K.2
-
5
-
-
0035215646
-
Low power system scheduling and synthesis
-
Nov.
-
N. K. Jha, "Low power system scheduling and synthesis," in Proc. Int. Conf. Computer-Aided Design, Nov. 2001, pp. 259-263.
-
(2001)
Proc. Int. Conf. Computer-aided Design
, pp. 259-263
-
-
Jha, N.K.1
-
6
-
-
0034477891
-
Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems
-
Nov.
-
J. Luo and N. K. Jha, "Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems," in Proc. Int. Conf. Computer-Aided Design, Nov. 2000, pp. 357-364.
-
(2000)
Proc. Int. Conf. Computer-aided Design
, pp. 357-364
-
-
Luo, J.1
Jha, N.K.2
-
7
-
-
0034785240
-
Considering power variations of DVS processing elements for energy minimization in distributed systems
-
Oct.
-
M. T. Schmitz and B. M. Al-Hashimi, "Considering power variations of DVS processing elements for energy minimization in distributed systems," in Proc. Int. Symp. System Synthesis, Oct. 2001, pp. 250-255.
-
(2001)
Proc. Int. Symp. System Synthesis
, pp. 250-255
-
-
Schmitz, M.T.1
Al-Hashimi, B.M.2
-
8
-
-
0032311886
-
On-line scheduling of hard real-time tasks on variable voltage processor
-
Nov.
-
I. Hong, M. Potkonjak, and M. B. Srivastava, "On-line scheduling of hard real-time tasks on variable voltage processor," in Proc. Int. Conf. Computer-Aided Design, Nov. 1998, pp. 653-656.
-
(1998)
Proc. Int. Conf. Computer-aided Design
, pp. 653-656
-
-
Hong, I.1
Potkonjak, M.2
Srivastava, M.B.3
-
9
-
-
84941360711
-
Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems
-
Jan.
-
J. Luo and N. K. Jha, "Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems," in Proc. Int. Conf. VLSI Design, Jan. 2003, pp. 369-375.
-
(2003)
Proc. Int. Conf. VLSI Design
, pp. 369-375
-
-
Luo, J.1
Jha, N.K.2
-
10
-
-
0032688679
-
Power conscious fixed priority scheduling for hard real-time systems
-
Jun.
-
Y. Shin and K. Choi, "Power conscious fixed priority scheduling for hard real-time systems," in Proc. Design Automation Conf., Jun. 1999, pp. 134-139.
-
(1999)
Proc. Design Automation Conf.
, pp. 134-139
-
-
Shin, Y.1
Choi, K.2
-
11
-
-
77954701375
-
-
[Online]
-
Intel XScale. [Online]. Available: http://www.intel.com
-
Intel XScale
-
-
-
12
-
-
33646907822
-
-
[Online]
-
Transmeta Crusoe. [Online]. Available: http://www.tranmeta.com
-
Transmeta Crusoe
-
-
-
13
-
-
78751680928
-
-
[Online]
-
AMD PowerNow!. [Online]. Available: http://www.amd.com
-
AMD PowerNow!
-
-
-
14
-
-
84962299846
-
Evaluating run-time techniques for leakage power reduction
-
Jan.
-
D. Duarte, Y. Tsai, N. Vijaykrishnan, and M. J. Irwin, "Evaluating run-time techniques for leakage power reduction," in Proc. Int. Conf. VLSI Design, Jan. 2002, pp. 31-38.
-
(2002)
Proc. Int. Conf. VLSI Design
, pp. 31-38
-
-
Duarte, D.1
Tsai, Y.2
Vijaykrishnan, N.3
Irwin, M.J.4
-
15
-
-
0036949134
-
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits
-
Aug.
-
A. Abdollahi, F. Fallah, and M. Pedram, "Runtime mechanisms for leakage current reduction in CMOS VLSI circuits," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 2002, pp. 475-478.
-
(2002)
Proc. Int. Symp. Low Power Electronics and Design
, pp. 475-478
-
-
Abdollahi, A.1
Fallah, F.2
Pedram, M.3
-
16
-
-
0032680122
-
Models and algorithms for bounds on leakage in CMOS circuits
-
Jun.
-
M. Johnson, D. Somasekhar, and K. Roy, "Models and algorithms for bounds on leakage in CMOS circuits," IEEE Trans. Computer-Aided Design, vol. 18, no. 6, pp. 714-725, Jun. 1999.
-
(1999)
IEEE Trans. Computer-aided Design
, vol.18
, Issue.6
, pp. 714-725
-
-
Johnson, M.1
Somasekhar, D.2
Roy, K.3
-
18
-
-
0030712582
-
A gate-level leakage power reduction method for ultra-low-power CMOS circuits
-
May
-
J. P. Halter and F. N. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," in Proc. Custom Integrated Circuits Conf., May 1997, pp. 475-478.
-
(1997)
Proc. Custom Integrated Circuits Conf.
, pp. 475-478
-
-
Halter, J.P.1
Najm, F.N.2
-
19
-
-
0029359285
-
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
-
Aug.
-
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, Issue.8
, pp. 847-854
-
-
Mutoh, S.1
Douseki, T.2
Matsuya, Y.3
Aoki, T.4
Shigematsu, S.5
Yamada, J.6
-
21
-
-
0034878684
-
Effectiveness of reverse body bias for leakage control in scaled dual-Vt CMOS ICs
-
Aug.
-
A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkari, and V. De, "Effectiveness of reverse body bias for leakage control in scaled dual-Vt CMOS ICs," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 2001, pp. 207-212.
-
(2001)
Proc. Int. Symp. Low Power Electronics and Design
, pp. 207-212
-
-
Keshavarzi, A.1
Ma, S.2
Narendra, S.3
Bloechel, B.4
Mistry, K.5
Ghani, T.6
Borkari, S.7
De, V.8
-
22
-
-
0030285492
-
22-D discrete cosine transform core processor with variable-threshold-voltage (VT) scheme
-
Nov.
-
22-D discrete cosine transform core processor with variable-threshold-voltage (VT) scheme," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1770-1779, Nov. 1996.
-
(1996)
IEEE J. Solid-state Circuits
, vol.31
, Issue.11
, pp. 1770-1779
-
-
Kuroda, T.1
Fujita, T.2
Mita, S.3
Nagamatsu, T.4
Yoshioka, S.5
Suzuki, K.6
Sano, F.7
Norishima, M.8
Murota, M.9
Kako, M.10
Kinugawa, M.11
Kakumu, M.12
Sakurai, T.13
-
25
-
-
0028755812
-
Automatic adjustment of threshold and supply voltages for minimum power consumption in CMOS digital circuits
-
Aug.
-
V. Kaenel, M. Pardoen, E. Dijkstra, and E. Vittoz, "Automatic adjustment of threshold and supply voltages for minimum power consumption in CMOS digital circuits," in Proc. Int. Symp. Low Power Electronics, Aug. 1994, pp. 78-79.
-
(1994)
Proc. Int. Symp. Low Power Electronics
, pp. 78-79
-
-
Kaenel, V.1
Pardoen, M.2
Dijkstra, E.3
Vittoz, E.4
-
26
-
-
0036114022
-
A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture
-
Feb.
-
M. Miyazaki, J. Kao, and A. Chandrakasan, "A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture," in Proc. Int. Conf. Solid-State Circuits, Feb. 2002, pp. 58-59.
-
(2002)
Proc. Int. Conf. Solid-state Circuits
, pp. 58-59
-
-
Miyazaki, M.1
Kao, J.2
Chandrakasan, A.3
-
27
-
-
0036917242
-
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
-
Nov.
-
S. M. Martin, K. Flautner, T. Mudge, and D. Blaauw, "Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads," in Proc. Int. Conf. Computer-Aided Design, Nov. 2002, pp. 721-725.
-
(2002)
Proc. Int. Conf. Computer-aided Design
, pp. 721-725
-
-
Martin, S.M.1
Flautner, K.2
Mudge, T.3
Blaauw, D.4
-
28
-
-
0025415048
-
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
-
Apr.
-
T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990.
-
(1990)
IEEE J. Solid-state Circuits
, vol.25
, Issue.2
, pp. 584-594
-
-
Sakurai, T.1
Newton, A.R.2
-
29
-
-
0019533480
-
Scheduling periodically occuring tasks on multiple processors
-
Feb.
-
E. L. Lawler and C. U. Martel, "Scheduling periodically occuring tasks on multiple processors," Inf. Process. Lett., vol. 7, pp. 9-12, Feb. 1981.
-
(1981)
Inf. Process. Lett.
, vol.7
, pp. 9-12
-
-
Lawler, E.L.1
Martel, C.U.2
-
30
-
-
0030386707
-
An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits
-
Aug.
-
A. Chatterjee, M. Nandakumar, and I. Chen, "An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 1996, pp. 145-150.
-
(1996)
Proc. Int. Symp. Low Power Electronics and Design
, pp. 145-150
-
-
Chatterjee, A.1
Nandakumar, M.2
Chen, I.3
-
31
-
-
0004051569
-
-
Ph.D. dissertation, Dept. Elect. Eng. Comp. Sci., Univ. California, Berkeley
-
A. Stratakos, "High-efficiency low-voltage DC-DC conversion for portable applications," Ph.D. dissertation, Dept. Elect. Eng. Comp. Sci., Univ. California, Berkeley, 1998.
-
(1998)
High-efficiency Low-voltage DC-DC Conversion for Portable Applications
-
-
Stratakos, A.1
-
32
-
-
0032308182
-
CORDS: Hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
-
Nov.
-
R. P. Dick and N. K. Jha, "CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems," in Proc. Int. Conf. Computer-Aided Design, Nov. 1998, pp. 62-68.
-
(1998)
Proc. Int. Conf. Computer-aided Design
, pp. 62-68
-
-
Dick, R.P.1
Jha, N.K.2
-
34
-
-
22544433779
-
-
[Online]
-
EEMBC. [Online], Available: http://www.eembc.com
-
-
-
-
35
-
-
0027540696
-
Fast allocation of processes in distributed and parallel systems
-
Feb.
-
C. M. Woodside and G. G. Monforton, "Fast allocation of processes in distributed and parallel systems," IEEE Trans. Parallel Distrib. Syst., vol. 4, no. 2, pp. 164-174, Feb. 1993.
-
(1993)
IEEE Trans. Parallel Distrib. Syst.
, vol.4
, Issue.2
, pp. 164-174
-
-
Woodside, C.M.1
Monforton, G.G.2
-
36
-
-
0031681657
-
TGFF: Task graphs for free
-
Mar.
-
R. P. Dick, D. L. Rhodes, and W. Wolf, "TGFF: Task graphs for free," in Proc. Int. Workshop Hardware/Software Codesign, Mar. 1998, pp. 97-101.
-
(1998)
Proc. Int. Workshop Hardware/Software Codesign
, pp. 97-101
-
-
Dick, R.P.1
Rhodes, D.L.2
Wolf, W.3
-
37
-
-
0030142084
-
Dynamic critical-path scheduling: An effective technique for allocating task graphs to multiprocessors
-
May
-
Y. Kwok and I. Ahmad, "Dynamic critical-path scheduling: An effective technique for allocating task graphs to multiprocessors," IEEE Trans. Parallel Distrib. Syst., vol. 7, no. 5, pp. 506-521, May 1996.
-
(1996)
IEEE Trans. Parallel Distrib. Syst.
, vol.7
, Issue.5
, pp. 506-521
-
-
Kwok, Y.1
Ahmad, I.2
|