Low power SRAM design using hierarchical divided bit-line approach

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 82-88

  Karandikar, Ashish ^a   Parhi, Keshab K ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC POTENTIAL; INTEGRATED CIRCUITS; TRANSISTORS;

HIERARCHICAL DIVIDED BIT LINE APPROACH; POWER CONSUMPTION;

RANDOM ACCESS STORAGE;

EID: 0032294454     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)