CACTI: An enhanced cache access and cycle time model

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 5, 1996, Pages 677-687

  Wilton, Steven J E ^b   Jouppi, Norman P ^a,c  

^a IEEE

^b UNIVERSITY OF TORONTO   (Canada)

^c HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; COMPARATOR CIRCUITS; COMPUTER SIMULATION; COMPUTER SOFTWARE; DECODING; MATHEMATICAL MODELS; TRANSISTORS;

COLUMN MULTIPLEXED BIT LINES; MEMORY SUBARRAYS; MULTIPLEXOR DRIVERS; TAG ARRAY; WORDLINE DRIVERS;

BUFFER STORAGE;

EID: 0030149507     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.509850     Document Type: Article

References (9)

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