Energy and performance improvements in microprocessor design using a loop cache

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1999, Pages 378-383

  Bellas, Nikolaos ^a   Hajj, Ibrahim ^a   Polychronopoulos, Constantine ^a   Stamoulis, George ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; ENERGY UTILIZATION; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; RESPONSE TIME (COMPUTER SYSTEMS); SIGNAL FILTERING AND PREDICTION; STORAGE ALLOCATION (COMPUTER);

FILTER CACHES; ON-CHIP CACHES;

VLSI CIRCUITS;

EID: 0033297639     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (9)