-
1
-
-
0003465202
-
The simplescalar tool set: Version 2.0
-
Dept. of CS, Univ. of Wisconsin-Madison, June and documentation for all Simplescalar releases (through version 3.0)
-
Burger, D. and Austin, T. M., "The SimpleScalar tool set: Version 2.0", Tech. Report, Dept. of CS, Univ. of Wisconsin-Madison, June 1997 and documentation for all Simplescalar releases (through version 3.0).
-
(1997)
Tech. Report
-
-
Burger, D.1
Austin, T.M.2
-
2
-
-
0035696763
-
Reducing the complexity of the register file in dynamic superscalar processor
-
Balasubramonian, R., Dwarkadas, S., Albonesi, D., "Reducing the Complexity of the Register File in Dynamic Superscalar Processor", in Proc. of MICRO-34, 2001.
-
(2001)
Proc. of MICRO-34
-
-
Balasubramonian, R.1
Dwarkadas, S.2
Albonesi, D.3
-
3
-
-
84949754375
-
Loose loops sink chips
-
Borch, E., Tune, E., Manne, S., Emer, J., "Loose Loops Sink Chips", in Proc. of HPCA, 2002.
-
(2002)
Proc. of HPCA
-
-
Borch, E.1
Tune, E.2
Manne, S.3
Emer, J.4
-
4
-
-
84944396166
-
Exploiting value locality in physical register files
-
Balakrishnan, S., Sohi, G., "Exploiting Value Locality in Physical Register Files", in Proc. of MICRO-36, 2003.
-
(2003)
Proc. of MICRO-36
-
-
Balakrishnan, S.1
Sohi, G.2
-
5
-
-
0002586775
-
Multiple-banked register file architecture
-
Cruz, J-L. et. al., "Multiple-Banked Register File Architecture", in Proc. of ISCA-27, 2000.
-
(2000)
Proc. of ISCA-27
-
-
Cruz, J.-L.1
-
6
-
-
0026984988
-
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors
-
Franklin, M., Sohi, G., "Register Traffic Analysis for Streamlining Inter-Operation Communication in Fine-Grain Parallel Processors", in Proc. of MICRO-25, 1992.
-
(1992)
Proc. of MICRO-25
-
-
Franklin, M.1
Sohi, G.2
-
7
-
-
0031599506
-
Virtual-physical registers
-
Gonzalez, A., Gonzalez, J., Valero, M., "Virtual-Physical Registers", in Proc. of HPCA-4, 1998.
-
(1998)
Proc. of HPCA-4
-
-
Gonzalez, A.1
Gonzalez, J.2
Valero, M.3
-
8
-
-
0010397844
-
Reducing register file power consumption by exploiting value lifetime characteristics
-
Hu, Z. and Martonosi, M., "Reducing Register File Power Consumption by Exploiting Value Lifetime Characteristics", in Workshop on Complexity-Effective Design (WCED), 2000.
-
(2000)
Workshop on Complexity-Effective Design (WCED)
-
-
Hu, Z.1
Martonosi, M.2
-
9
-
-
0003278283
-
The microarchitecture of the pentium 4 processor
-
Hinton, G., et.al., "The Microarchitecture of the Pentium 4 Processor", Intel Technology Journal, Q1, 2001.
-
(2001)
Intel Technology Journal
, vol.Q1
-
-
Hinton, G.1
-
10
-
-
0035189552
-
In-line interrupt handling for software-managed TLBs
-
Jaleel A. and Jacob B. "In-line interrupt handling for software-managed TLBs." in Proc. of ICCD-19, 2001.
-
(2001)
Proc. of ICCD-19
-
-
Jaleel, A.1
Jacob, B.2
-
11
-
-
0032315402
-
A novel renaming scheme to exploit value temporal locality through physical register reuse and unification
-
Jourdan, S., Ronen, R., Bekerman, M., Shomar, B. and Yoaz, A., "A Novel Renaming Scheme to Exploit Value Temporal Locality through Physical Register Reuse and Unification", in Proc. of MICRO-31, 1998.
-
(1998)
Proc. of MICRO-31
-
-
Jourdan, S.1
Ronen, R.2
Bekerman, M.3
Shomar, B.4
Yoaz, A.5
-
12
-
-
0032639289
-
The alpha 21264 microprocessor
-
Kessler, R.E., "The Alpha 21264 Microprocessor", in Micro, 19(2), 1999.
-
(1999)
Micro
, vol.19
, Issue.2
-
-
Kessler, R.E.1
-
13
-
-
1142280977
-
Reducing register ports using delayed write-back queues and operand pre-fetch
-
Kim, N., Mudge, T., "Reducing Register Ports Using Delayed Write-Back Queues and Operand Pre-Fetch", in ICS, 2003.
-
(2003)
ICS
-
-
Kim, N.1
Mudge, T.2
-
14
-
-
84948992629
-
Cherry: Checkpointed early resource recycling in out-of-order microprocessors
-
Martinez, J., Renau, J., Huang, M., Prvulovich, M., Torrellas, J., "Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors", in Proc. of MICRO-35, 2002.
-
(2002)
Proc. of MICRO-35
-
-
Martinez, J.1
Renau, J.2
Huang, M.3
Prvulovich, M.4
Torrellas, J.5
-
15
-
-
0028056592
-
Register renaming and dynamic speculation: An alternative approach
-
Moudgill, M., Pingali, K., Vassiliadis, S., "Register Renaming and Dynamic Speculation: An Alternative Approach", in Proc. of MICRO-26, 1993.
-
Proc. of MICRO-26, 1993
-
-
Moudgill, M.1
Pingali, K.2
Vassiliadis, S.3
-
16
-
-
84948464914
-
Hardware schemes for early register release
-
Monreal, T., Vinals, V., Gonzalez, A., Valero, M. "Hardware Schemes for Early Register Release", in ICPP-02, 2002.
-
(2002)
ICPP-02
-
-
Monreal, T.1
Vinals, V.2
Gonzalez, A.3
Valero, M.4
-
17
-
-
41349090027
-
Reducing register ports for higher speed and lower energy
-
Park, I., Powell, M., Vijaykumar, T., "Reducing Register Ports for Higher Speed and Lower Energy", in MICRO, 2002.
-
(2002)
MICRO
-
-
Park, I.1
Powell, M.2
Vijaykumar, T.3
-
18
-
-
21644454547
-
Dynamically reducing pressure on the physical register file through simple register sharing
-
Tran, N., et.al., "Dynamically Reducing Pressure on the Physical Register File through Simple Register Sharing", in Proc. of ISPASS-2004, 2004.
-
(2004)
Proc. of ISPASS-2004
-
-
Tran, N.1
-
19
-
-
0029749713
-
A scalable register file architecture for dynamically scheduled processors
-
Wallase, S., Bagherzadeh, N., "A Scalable Register File Architecture for Dynamically Scheduled Processors", in Proc. of PACT-5, 1996.
-
Proc. of PACT-5, 1996
-
-
Wallase, S.1
Bagherzadeh, N.2
-
20
-
-
0030129806
-
The MIPS R10000 superscalar microprocessor
-
April
-
Yeager, K., "The MIPS R10000 Superscalar Microprocessor", IEEE Micro, Vol. 16, No 2, April, 1996.
-
(1996)
IEEE Micro
, vol.16
, Issue.2
-
-
Yeager, K.1
-
21
-
-
0003582432
-
Dynamic cluster assignment mechanisms
-
Canal, R., Parserisa, J.M., Gonzalez, A., "Dynamic Cluster Assignment Mechanisms", in Proc. of HPCA-6, 2000.
-
(2000)
Proc. of HPCA-6
-
-
Canal, R.1
Parserisa, J.M.2
Gonzalez, A.3
-
22
-
-
0031374601
-
The multicluster architecture: Reducing cycle time through partitioning
-
Farkas, K., Chow, P., Jouppi, N., Vranesic, Z., "The Multicluster Architecture: Reducing Cycle Time Through Partitioning", in Proc. of MICRO-30, 1997.
-
(1997)
Proc. of MICRO-30
-
-
Farkas, K.1
Chow, P.2
Jouppi, N.3
Vranesic, Z.4
-
23
-
-
0012574251
-
Profile-based dynamic voltage scheduling using program checkpoints in COPPER framework
-
Azevedo, A., et.al., "Profile-based Dynamic Voltage Scheduling using Program Checkpoints in COPPER Framework", in Proceedings of DATE, 2002.
-
Proceedings of DATE, 2002
-
-
Azevedo, A.1
-
25
-
-
0031379698
-
Exploiting dead value information
-
Martin, M., Roth, A., Fischer, C., "Exploiting Dead Value Information", in Proc. Of MICRO-30, 1997.
-
Proc. of MICRO-30, 1997
-
-
Martin, M.1
Roth, A.2
Fischer, C.3
-
26
-
-
4644269726
-
Use-based register caching with decoupled indexing
-
Butts, A., Sohi, G., "Use-Based Register Caching with Decoupled Indexing", in Proc. of ISCA, 2004.
-
Proc. of ISCA, 2004
-
-
Butts, A.1
Sohi, G.2
-
27
-
-
0032778066
-
Dynamically exploiting narrow width operands to improve processor power and performance
-
Brooks, D. and Martonosi, M., "Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance", in Proc. of HPCA, 1999.
-
Proc. of HPCA, 1999
-
-
Brooks, D.1
Martonosi, M.2
-
29
-
-
21644446655
-
Dynamic zero compression for cache energy reduction
-
Villa, L., Zhang, M. and Asanovic, K., "Dynamic Zero Compression for Cache Energy Reduction", in MICO 2000.
-
MICO 2000
-
-
Villa, L.1
Zhang, M.2
Asanovic, K.3
-
30
-
-
3042523075
-
Software-controlled operand gating
-
Canal, R., Gonzalez, A., Smith, J., "Software-Controlled Operand Gating", in Proc. of the Intl. Symp. On Code Generation and Optimization, 2004.
-
(2004)
Proc. of the Intl. Symp. on Code Generation and Optimization
-
-
Canal, R.1
Gonzalez, A.2
Smith, J.3
-
31
-
-
69249220832
-
Exploiting data-width locality to increase superscalar execution bandwidth
-
Loh, G., "Exploiting Data-Width Locality to Increase Superscalar Execution Bandwidth", in MICRO-35, 2002.
-
(2002)
MICRO-35
-
-
Loh, G.1
-
33
-
-
0001876657
-
Delaying physical register allocation through virtual physical registers
-
Monreal, T., et.al., "Delaying Physical Register Allocation Through Virtual Physical Registers", in Proc. of MICRO-34 1999.
-
Proc. of MICRO-34 1999
-
-
Monreal, T.1
-
35
-
-
0346295346
-
Bitvalue inference: Detecting and exploiting narrow bitwidth computations
-
Budiu, M., et.al., "BitValue inference: Detecting and Exploiting Narrow Bitwidth Computations", in Proceedings of EuroPar 2000.
-
Proceedings of EuroPar 2000
-
-
Budiu, M.1
-
36
-
-
47349088015
-
Accurate static branch prediction by value range propagation
-
Patterson, J., "Accurate Static Branch Prediction by Value Range Propagation", in Proc. of PLDI, 1995.
-
Proc. of PLDI, 1995
-
-
Patterson, J.1
-
37
-
-
21644448592
-
Bitwidth analysis with application to silicon compilation
-
Stephenson, M., et.al., "Bitwidth Analysis with Application to Silicon Compilation", in Proc. of PLDI, 2001.
-
(2001)
Proc. of PLDI
-
-
Stephenson, M.1
-
38
-
-
0034863755
-
A system-level energy minimization approach using datapath width optimization
-
Cao, Y., "A System-Level Energy Minimization Approach Using Datapath Width Optimization", in Proc. of ISLPED, 2001.
-
Proc. of ISLPED, 2001
-
-
Cao, Y.1
-
39
-
-
0033691758
-
Table size reduction for data value predictors by exploiting narrow width values
-
Sato, T., Arita, I., "Table Size Reduction for Data Value Predictors by Exploiting Narrow Width Values", in Proc. of ICS, 2000.
-
Proc. of ICS, 2000
-
-
Sato, T.1
Arita, I.2
-
41
-
-
17644379115
-
Increasing processor performance through early register release
-
Ergin, O., Balkan,D., Ponomarev, D., Ghose, K., "Increasing Processor Performance Through Early Register Release", in Proceedings of ICCD, 2004.
-
Proceedings of ICCD, 2004
-
-
Ergin, O.1
Balkan, D.2
Ponomarev, D.3
Ghose, K.4
-
42
-
-
17644367579
-
Defining wakeup width for efficient dynamic scheduling
-
Aggarwal, A., Franklin, M., Ergin, O., "Defining Wakeup Width for Efficient Dynamic Scheduling", in ICCD 2004.
-
ICCD 2004
-
-
Aggarwal, A.1
Franklin, M.2
Ergin, O.3
-
45
-
-
21644454860
-
Selective writeback: Improving processor performance and energy efficiency
-
Balkan D., Ergin O., Ponomarev D., Ghose K. "Selective Writeback: Improving Processor Performance and Energy Efficiency", in Proc. of IBM p=ac2 conference, 2004.
-
Proc. of IBM P=ac2 Conference, 2004
-
-
Balkan, D.1
Ergin, O.2
Ponomarev, D.3
Ghose, K.4
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