-
2
-
-
0036294454
-
Drowsy caches: Simple techniques for reducing leakage power
-
K. Flautner, et al. "Drowsy Caches: Simple Techniques for Reducing Leakage Power," In Proc. ISCA 29, 2002.
-
Proc. ISCA 29, 2002
-
-
Flautner, K.1
-
3
-
-
0033645390
-
Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories
-
Michael Powell et al. "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories," In Proc. ISLPED 2000.
-
Proc. ISLPED 2000
-
-
Powell, M.1
-
4
-
-
0034856732
-
Cache decay: Exploiting generational behavior to reduce cache leakage power
-
S. Kaxiras, Z. Hu, M. Martonosi, "Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power," In Proc. ISCA 28, 2001.
-
(2001)
Proc. ISCA 28
-
-
Kaxiras, S.1
Hu, Z.2
Martonosi, M.3
-
5
-
-
28444455496
-
Decaying 4T thermal/leakage sensors
-
S. Kaxiras, Polychronis Xekalakis "Decaying 4T Thermal/Leakage Sensors," In Proc. ISLPED, 2004.
-
(2004)
Proc. ISLPED
-
-
Kaxiras, S.1
Xekalakis, P.2
-
6
-
-
28444495894
-
On the limits of leakage power reduction in caches
-
Yan Meng, et al. "On the Limits of Leakage Power Reduction in Caches," In Proc. HPCA-11, 2004.
-
(2004)
Proc. HPCA-11
-
-
Meng, Y.1
-
7
-
-
3042656888
-
State-preserving vs. non-state-preserving leakage control in caches
-
Feb.
-
Yingmin Li et al. "State-Preserving vs. Non-State-Preserving Leakage Control in Caches," In Proc. of the 2004 DATE Conference, pp. 22-27, Feb. 2004.
-
(2004)
Proc. of the 2004 DATE Conference
, pp. 22-27
-
-
Li, Y.1
-
8
-
-
0032297487
-
The alpha 21264 microprocessor architecture
-
Oct.
-
R. E. Kessler, et al. "The Alpha 21264 microprocessor architecture," In Proc. ICCD 1998, pages 90-95, Oct. 1998.
-
(1998)
Proc. ICCD 1998
, pp. 90-95
-
-
Kessler, R.E.1
-
9
-
-
0031635212
-
A technique for StandbyLeakage reduction in high-performance circuits
-
Y. Ye, S. Borkar, and V. De, "A Technique for StandbyLeakage Reduction in High-Performance Circuits," Symp.ofYLSI Circuits, pp. 40-41, 1998.
-
(1998)
Symp.ofYLSI Circuits
, pp. 40-41
-
-
Ye, Y.1
Borkar, S.2
De, V.3
-
10
-
-
28444435065
-
The simulation and evaluation of dynamic voltage scaling algorithms
-
T. Pering, et al. "The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms," In Proc. ISLPED 1998.
-
Proc. ISLPED 1998
-
-
Pering, T.1
-
11
-
-
1542359161
-
Effectiveness and scalling trends of leakage control techniques for sub-130nm CMOS technologies
-
Bhaskar Chatterjee, et al. "Effectiveness and Scalling Trends of Leakage Control Techniques for Sub-130nm CMOS Technologies," In Proc. ISLPED 2003.
-
Proc. ISLPED 2003
-
-
Chatterjee, B.1
-
12
-
-
0033680440
-
High-perfomance low-power CMOS circuits using multiple channel length and multiple oxide thickness
-
N. Sirisantana, L. Wei, and K. Roy, "High-Perfomance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness," in Proc. ICCD, 2000.
-
(2000)
Proc. ICCD
-
-
Sirisantana, N.1
Wei, L.2
Roy, K.3
-
13
-
-
0009633182
-
Adaptive mode control: A static-power-efficient cache design
-
Sept.
-
H. Zhou, et al. "Adaptive mode control: A static-power-efficient cache design," In Proc. PACT 2001, Sept. 2001.
-
(2001)
Proc. PACT 2001
-
-
Zhou, H.1
-
14
-
-
0347894347
-
Adaptive cache decay using formal feedback control
-
May
-
S. Velusamy, et al. "Adaptive cache decay using formal feedback control," In Proc. WMPI-2, May 2002.
-
(2002)
Proc. WMPI-2
-
-
Velusamy, S.1
-
15
-
-
84932130886
-
LargerthanVdd forward body bias in sub0.5V nanoscale CMOS
-
Hari Ananthan, et al. "LargerthanVdd Forward Body Bias in Sub0.5V Nanoscale CMOS," In Proc. ISLPED, 2004.
-
(2004)
Proc. ISLPED
-
-
Ananthan, H.1
-
16
-
-
0029359285
-
1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS
-
S. Mutah, et al. "1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS," IEEE Journal of Solid-State Circuits, 30(8):847-853, 1995.
-
(1995)
IEEE Journal of Solid-state Circuits
, vol.30
, Issue.8
, pp. 847-853
-
-
Mutah, S.1
-
17
-
-
0036049095
-
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering
-
M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry "Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering," In Proc. DAC 2002.
-
Proc. DAC 2002
-
-
Anis, M.1
Areibi, S.2
Mahmoud, M.3
Elmasry, M.4
-
18
-
-
0031635596
-
Design and optimization of low voltage high performance dual threshold CMOS circuits
-
Liqiong Wei, et al. "Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits," In Proc. of the 35th annual conference on Design Automation.
-
Proc. of the 35th Annual Conference on Design Automation
-
-
Wei, L.1
-
19
-
-
34249306904
-
Hotleakage: An architectural, temperature-aware model of subthreshold and gate leakage
-
CS Dept., University of Virginia, Mar.
-
Y. Zhang, et al. "Hotleakage: An architectural, temperature-aware model of subthreshold and gate leakage," Tech. Report CS-2003-05, CS Dept., University of Virginia, Mar. 2003.
-
(2003)
Tech. Report
, vol.CS-2003-05
-
-
Zhang, Y.1
|