Integrated analysis of power and performance for pipelined microprocessors

IEEE Transactions on Computers

Volumn 53, Issue 8, 2004, Pages 1004-1016

  Zyuban, Victor ^a   Brooks, David ^b   Srinivasan, Viji ^a   Gschwind, Michael ^a   Bose, Pradip ^a   Strenski, Philip N ^a   Emma, Philip G ^a  

^a IEEE   (United States)

^b HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION; PERFORMANCE; PIPELINE PROCESSING SYSTEMS; RISK ASSESSMENT; SENSITIVITY ANALYSIS; TIMING CIRCUITS;

ENERGY AWARE SYSTEMS; ENERGY MODELS; PERFORMANCE ANALYSIS; PIPELINED MICROPROCESSORS;

MICROCOMPUTERS;

EID: 3242680845     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.46     Document Type: Article

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