Dynamically exploiting narrow width operands to improve processor power and performance

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 1999, Pages 13-22

  Brooks, David ^a   Martonosi, Margaret ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER SELECTION AND EVALUATION; DIGITAL ARITHMETIC; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS);

INTEGER ARITHMETICS; NARROW WIDTH OPERANDS;

COMPUTER ARCHITECTURE;

EID: 0032778066     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/hpca.1999.744314     Document Type: Conference Paper

References (21)